1# Core 2 possible unit masks 2# 3name:zero type:mandatory default:0x0 4 0x0 No unit mask 5#name:one type:mandatory default:0x1 6# 0x1 No unit mask 7name:two type:mandatory default:0x2 8 0x2 No unit mask 9name:x0f type:mandatory default:0xf 10 0xf No unit mask 11name:x10 type:mandatory default:0x10 12 0x10 No unit mask 13#name:x20 type:mandatory default:0x20 14# 0x20 No unit mask 15#name:x40 type:mandatory default:0x40 16# 0x40 No unit mask 17name:x41 type:mandatory default:0x41 18 0x41 No unit mask 19name:x4f type:mandatory default:0x4f 20 0x4f No unit mask 21name:xc0 type:mandatory default:0xc0 22 0xc0 No unit mask 23name:nonhlt type:exclusive default:0x0 24 0x0 Unhalted core cycles 25 0x1 Unhalted bus cycles 26 0x2 Unhalted bus cycles of this core while the other core is halted 27name:mesi type:bitmask default:0x0f 28 0x08 (M)ESI: Modified 29 0x04 M(E)SI: Exclusive 30 0x02 ME(S)I: Shared 31 0x01 MES(I): Invalid 32name:sse_prefetch type:exclusive default:0x0 33 0x00 prefetch NTA instructions executed. 34 0x01 prefetch T1 instructions executed. 35 0x02 prefetch T1 and T2 instructions executed. 36 0x03 SSE weakly-ordered stores 37name:simd_instr_type_exec type:bitmask default:0x3f 38 0x01 SIMD packed multiplies 39 0x02 SIMD packed shifts 40 0x04 SIMD pack operations 41 0x08 SIMD unpack operations 42 0x10 SIMD packed logical 43 0x20 SIMD packed arithmetic 44 0x3f all of the above 45name:mmx_trans type:bitmask default:0x3 46 0x01 float->MMX transitions 47 0x02 MMX->float transitions 48name:sse_miss type:exclusive default:0x0 49 0x00 PREFETCHNTA 50 0x01 PREFETCHT0 51 0x02 PREFETCHT1/PREFETCHT2 52name:load_block type:bitmask default:0x3e 53 0x02 STA Loads blocked by a preceding store with unknown address. 54 0x04 STD Loads blocked by a preceding store with unknown data. 55 0x08 OVERLAP_STORE Loads that partially overlap an earlier store, or 4K aliased with a previous store. 56 0x10 UNTIL_RETIRE Loads blocked until retirement. 57 0x20 L1D Loads blocked by the L1 data cache. 58name:store_block type:bitmask default:0x0b 59 0x01 SB_DRAIN_CYCLES Cycles while stores are blocked due to store buffer drain. 60 0x02 ORDER Cycles while store is waiting for a preceding store to be globally observed. 61 0x08 NOOP A store is blocked due to a conflict with an external or internal snoop. 62name:dtlb_miss type:bitmask default:0x0f 63 0x01 ANY Memory accesses that missed the DTLB. 64 0x02 MISS_LD DTLB misses due to load operations. 65 0x04 L0_MISS_LD L0 DTLB misses due to load operations. 66 0x08 MISS_ST TLB misses due to store operations. 67name:memory_dis type:exclusive default:0x01 68 0x01 RESET Memory disambiguation reset cycles. 69 0x02 SUCCESS Number of loads that were successfully disambiguated. 70name:page_walks type:exclusive default:0x02 71 0x01 COUNT Number of page-walks executed. 72 0x02 CYCLES Duration of page-walks in core cycles. 73name:delayed_bypass type:exclusive default:0x00 74 0x00 FP Delayed bypass to FP operation. 75 0x01 SIMD Delayed bypass to SIMD operation. 76 0x02 LOAD Delayed bypass to load operation. 77name:core type:exclusive default:0x40 78 0xc0 All cores 79 0x40 This core 80name:core_prefetch type:bitmask default:0x70 81 0xc0 core: all cores 82 0x40 core: this core 83 0x30 prefetch: all inclusive 84 0x10 prefetch: Hardware prefetch only 85 0x00 prefetch: exclude hardware prefetch 86name:core_mesi type:bitmask default:0x4f 87 0xc0 core: all cores 88 0x40 core: this core 89 0x08 (M)ESI: Modified 90 0x04 M(E)SI: Exclusive 91 0x02 ME(S)I: Shared 92 0x01 MES(I): Invalid 93name:core_prefetch_mesi type:bitmask default:0x7f 94 0xc0 core: all cores 95 0x40 core: this core 96 0x30 prefetch: all inclusive 97 0x10 prefetch: Hardware prefetch only 98 0x00 prefetch: exclude hardware prefetch 99 0x08 (M)ESI: Modified 100 0x04 M(E)SI: Exclusive 101 0x02 ME(S)I: Shared 102 0x01 MES(I): Invalid 103name:l1d_split type:exclusive default:0x1 104 0x1 split loads 105 0x2 split stores 106name:bus_agents type:exclusive default:0x00 107 0x00 this agent 108 0x20 include all agents 109name:core_and_bus_agents type:bitmask default:0x40 110 0xc0 core: all cores 111 0x40 core: this core 112 0x00 bus: this agent 113 0x20 bus: include all agents 114name:bus_agents_and_snoop type:bitmask default:0x0b 115 0x00 bus: this agent 116 0x20 bus: include all agents 117 0x08 snoop: HITM snoops 118 0x02 snoop: HIT snoops 119 0x01 snoop: CLEAN snoops 120name:core_and_snoop type:bitmask default:0x40 121 0xc0 core: all cores 122 0x40 core: this core 123 0x01 snoop: CMP2I snoops 124 0x02 snoop: CMP2S snoops 125name:itlb_miss type:bitmask default:0x12 126 0x02 ITLB small page misses 127 0x10 ITLB large page misses 128 0x40 ITLB flushes 129name:macro_insts type:bitmask default:0x09 130 0x01 Instructions decoded 131 0x08 CISC Instructions decoded 132name:esp type:bitmask default:0x01 133 0x01 ESP register content synchronizations 134 0x02 ESP register automatic additions 135name:inst_retired type:bitmask default:0x00 136 0x00 Any 137 0x01 Loads 138 0x02 Stores 139 0x04 Other 140name:x87_ops_retired type:exclusive default:0xfe 141 0x01 FXCH instructions retired 142 0xfe Retired floating-point computational operations (precise) 143name:uops_retired type:bitmask default:0x0f 144 0x01 Fused load+op or load+indirect branch retired 145 0x02 Fused store address + data retired 146 0x04 Retired instruction pairs fused into one micro-op 147 0x07 Fused micro-ops retired 148 0x08 Non-fused micro-ops retired 149 0x0f Micro-ops retired 150name:machine_nukes type:bitmask default:0x05 151 0x01 Self-Modifying Code detected 152 0x04 Execution pipeline restart due to memory ordering conflict or memory disambiguation misprediction 153name:br_inst_retired type:bitmask default:0xa 154 0x01 predicted not-taken 155 0x02 mispredicted not-taken 156 0x04 predicted taken 157 0x08 mispredicted taken 158name:cycles_int_masked type:exclusive default:0x02 159 0x01 Interrupts disabled 160 0x02 Interrupts pending and disabled 161name:simd_inst_retired type:bitmask default:0x1f 162 0x01 Retired SSE packed-single instructions 163 0x02 Retired SSE scalar-single instructions 164 0x04 Retired SSE2 packed-double instructions 165 0x08 Retired SSE2 scalar-double instructions 166 0x10 Retired SSE2 vector integer instructions 167 0x1f Retired Streaming SIMD instructions (precise event) 168name:simd_comp_inst_retired type:bitmask default:0xf 169 0x01 Retired computational SSE packed-single instructions 170 0x02 Retired computational SSE scalar-single instructions 171 0x04 Retired computational SSE2 packed-double instructions 172 0x08 Retired computational SSE2 scalar-double instructions 173name:mem_load_retired type:exclusive default:0x01 174 0x01 Retired loads that miss the L1 data cache (precise event) 175 0x02 L1 data cache line missed by retired loads (precise event) 176 0x04 Retired loads that miss the L2 cache (precise event) 177 0x08 L2 cache line missed by retired loads (precise event) 178 0x10 Retired loads that miss the DTLB (precise event) 179name:rat_stalls type:bitmask default:0xf 180 0x01 ROB read port 181 0x02 Partial register 182 0x04 Flag 183 0x08 FPU status word 184 0x0f All RAT 185name:seg_regs type:bitmask default:0x0f 186 0x01 ES 187 0x02 DS 188 0x04 FS 189 0x08 GS 190name:resource_stalls type:bitmask default:0x0f 191 0x01 when the ROB is full 192 0x02 during which the RS is full 193 0x04 during which the pipeline has exceeded the load or store limit or is waiting to commit all stores 194 0x08 due to FPU control word write 195 0x10 due to branch misprediction 196