1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #define TCG_TARGET_SPARC 1
25
26 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
27 #define TCG_TARGET_REG_BITS 64
28 #else
29 #define TCG_TARGET_REG_BITS 32
30 #endif
31
32 #define TCG_TARGET_WORDS_BIGENDIAN
33
34 #define TCG_TARGET_NB_REGS 32
35
36 enum {
37 TCG_REG_G0 = 0,
38 TCG_REG_G1,
39 TCG_REG_G2,
40 TCG_REG_G3,
41 TCG_REG_G4,
42 TCG_REG_G5,
43 TCG_REG_G6,
44 TCG_REG_G7,
45 TCG_REG_O0,
46 TCG_REG_O1,
47 TCG_REG_O2,
48 TCG_REG_O3,
49 TCG_REG_O4,
50 TCG_REG_O5,
51 TCG_REG_O6,
52 TCG_REG_O7,
53 TCG_REG_L0,
54 TCG_REG_L1,
55 TCG_REG_L2,
56 TCG_REG_L3,
57 TCG_REG_L4,
58 TCG_REG_L5,
59 TCG_REG_L6,
60 TCG_REG_L7,
61 TCG_REG_I0,
62 TCG_REG_I1,
63 TCG_REG_I2,
64 TCG_REG_I3,
65 TCG_REG_I4,
66 TCG_REG_I5,
67 TCG_REG_I6,
68 TCG_REG_I7,
69 };
70
71 #define TCG_CT_CONST_S11 0x100
72 #define TCG_CT_CONST_S13 0x200
73
74 /* used for function call generation */
75 #define TCG_REG_CALL_STACK TCG_REG_I6
76 #ifdef __arch64__
77 // Reserve space for AREG0
78 #define TCG_TARGET_STACK_MINFRAME (176 + 4 * (int)sizeof(long) + \
79 TCG_STATIC_CALL_ARGS_SIZE)
80 #define TCG_TARGET_CALL_STACK_OFFSET (2047 - 16)
81 #define TCG_TARGET_STACK_ALIGN 16
82 #else
83 // AREG0 + one word for alignment
84 #define TCG_TARGET_STACK_MINFRAME (92 + (2 + 1) * (int)sizeof(long) + \
85 TCG_STATIC_CALL_ARGS_SIZE)
86 #define TCG_TARGET_CALL_STACK_OFFSET TCG_TARGET_STACK_MINFRAME
87 #define TCG_TARGET_STACK_ALIGN 8
88 #endif
89
90 #ifdef __arch64__
91 #define TCG_TARGET_EXTEND_ARGS 1
92 #endif
93
94 /* optional instructions */
95 #define TCG_TARGET_HAS_div_i32
96 // #define TCG_TARGET_HAS_rot_i32
97 // #define TCG_TARGET_HAS_ext8s_i32
98 // #define TCG_TARGET_HAS_ext16s_i32
99 // #define TCG_TARGET_HAS_ext8u_i32
100 // #define TCG_TARGET_HAS_ext16u_i32
101 // #define TCG_TARGET_HAS_bswap16_i32
102 // #define TCG_TARGET_HAS_bswap32_i32
103 #define TCG_TARGET_HAS_neg_i32
104 #define TCG_TARGET_HAS_not_i32
105 #define TCG_TARGET_HAS_andc_i32
106 #define TCG_TARGET_HAS_orc_i32
107 // #define TCG_TARGET_HAS_eqv_i32
108 // #define TCG_TARGET_HAS_nand_i32
109 // #define TCG_TARGET_HAS_nor_i32
110
111 #if TCG_TARGET_REG_BITS == 64
112 #define TCG_TARGET_HAS_div_i64
113 // #define TCG_TARGET_HAS_rot_i64
114 // #define TCG_TARGET_HAS_ext8s_i64
115 // #define TCG_TARGET_HAS_ext16s_i64
116 #define TCG_TARGET_HAS_ext32s_i64
117 // #define TCG_TARGET_HAS_ext8u_i64
118 // #define TCG_TARGET_HAS_ext16u_i64
119 #define TCG_TARGET_HAS_ext32u_i64
120 // #define TCG_TARGET_HAS_bswap16_i64
121 // #define TCG_TARGET_HAS_bswap32_i64
122 // #define TCG_TARGET_HAS_bswap64_i64
123 #define TCG_TARGET_HAS_neg_i64
124 #define TCG_TARGET_HAS_not_i64
125 #define TCG_TARGET_HAS_andc_i64
126 #define TCG_TARGET_HAS_orc_i64
127 // #define TCG_TARGET_HAS_eqv_i64
128 // #define TCG_TARGET_HAS_nand_i64
129 // #define TCG_TARGET_HAS_nor_i64
130 #endif
131
132 /* Note: must be synced with dyngen-exec.h */
133 #ifdef CONFIG_SOLARIS
134 #define TCG_AREG0 TCG_REG_G2
135 #elif defined(__sparc_v9__)
136 #define TCG_AREG0 TCG_REG_G5
137 #else
138 #define TCG_AREG0 TCG_REG_G6
139 #endif
140
flush_icache_range(unsigned long start,unsigned long stop)141 static inline void flush_icache_range(unsigned long start, unsigned long stop)
142 {
143 unsigned long p;
144
145 p = start & ~(8UL - 1UL);
146 stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
147
148 for (; p < stop; p += 8)
149 __asm__ __volatile__("flush\t%0" : : "r" (p));
150 }
151