2355     unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)  in LowerINTRINSIC_WO_CHAIN()  local
2357     return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),  in LowerINTRINSIC_WO_CHAIN()
4829   unsigned NewOpc = 0;  in LowerMUL()  local
4834     NewOpc = ARMISD::VMULLs;  in LowerMUL()
4839       NewOpc = ARMISD::VMULLu;  in LowerMUL()
4844         NewOpc = ARMISD::VMULLs;  in LowerMUL()
4847         NewOpc = ARMISD::VMULLu;  in LowerMUL()
4851         NewOpc = ARMISD::VMULLu;  in LowerMUL()
4856     if (!NewOpc) {  in LowerMUL()
4875     return DAG.getNode(NewOpc, DL, VT, Op0, Op1);  in LowerMUL()
4890                      DAG.getNode(NewOpc, DL, VT,  in LowerMUL()
4892                      DAG.getNode(NewOpc, DL, VT,  in LowerMUL()
6243     unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?  in EmitInstrWithCustomInserter()  local
6253     BuildMI(*BB, MI, dl, TII->get(NewOpc))  in EmitInstrWithCustomInserter()
6267     unsigned NewOpc;  in EmitInstrWithCustomInserter()  local
6270     case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;  in EmitInstrWithCustomInserter()
6271     case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;  in EmitInstrWithCustomInserter()
6272     case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;  in EmitInstrWithCustomInserter()
6274     MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));  in EmitInstrWithCustomInserter()
6590   unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());  in AdjustInstrPostInstrSelection()  local
6591   if (NewOpc) {  in AdjustInstrPostInstrSelection()
6594     MCID = &TII->get(NewOpc);  in AdjustInstrPostInstrSelection()
6609     assert(!NewOpc && "Optional cc_out operand required");  in AdjustInstrPostInstrSelection()
6628     assert(!NewOpc && "Optional cc_out operand required");  in AdjustInstrPostInstrSelection()
7643     unsigned NewOpc = 0;  in CombineBaseUpdate()  local
7649       case Intrinsic::arm_neon_vld1:     NewOpc = ARMISD::VLD1_UPD;  in CombineBaseUpdate()
7651       case Intrinsic::arm_neon_vld2:     NewOpc = ARMISD::VLD2_UPD;  in CombineBaseUpdate()
7653       case Intrinsic::arm_neon_vld3:     NewOpc = ARMISD::VLD3_UPD;  in CombineBaseUpdate()
7655       case Intrinsic::arm_neon_vld4:     NewOpc = ARMISD::VLD4_UPD;  in CombineBaseUpdate()
7657       case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;  in CombineBaseUpdate()
7659       case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;  in CombineBaseUpdate()
7661       case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;  in CombineBaseUpdate()
7663       case Intrinsic::arm_neon_vst1:     NewOpc = ARMISD::VST1_UPD;  in CombineBaseUpdate()
7665       case Intrinsic::arm_neon_vst2:     NewOpc = ARMISD::VST2_UPD;  in CombineBaseUpdate()
7667       case Intrinsic::arm_neon_vst3:     NewOpc = ARMISD::VST3_UPD;  in CombineBaseUpdate()
7669       case Intrinsic::arm_neon_vst4:     NewOpc = ARMISD::VST4_UPD;  in CombineBaseUpdate()
7671       case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;  in CombineBaseUpdate()
7673       case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;  in CombineBaseUpdate()
7675       case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;  in CombineBaseUpdate()
7682       case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;  in CombineBaseUpdate()
7683       case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;  in CombineBaseUpdate()
7684       case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;  in CombineBaseUpdate()
7727     SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,  in CombineBaseUpdate()
7762   unsigned NewOpc = 0;  in CombineVLDDUP()  local
7766     NewOpc = ARMISD::VLD2DUP;  in CombineVLDDUP()
7769     NewOpc = ARMISD::VLD3DUP;  in CombineVLDDUP()
7772     NewOpc = ARMISD::VLD4DUP;  in CombineVLDDUP()
7801   SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,  in CombineVLDDUP()