Lines Matching refs:src2

20            (ins VR128:$src1, VR128:$src2),
21            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
24            (ins VR128:$src1, f128mem:$src2),
25            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
28            (ins VR256:$src1, VR256:$src2),
29            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
32            (ins VR256:$src1, f256mem:$src2),
33            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
71            (ins VR128:$src1, VR128:$src2),
72            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
75            (ins VR128:$src1, x86memop:$src2),
76            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
104            (ins VR128:$src1, VR128:$src2, VR128:$src3),
106            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
108              (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
110            (ins VR128:$src1, VR128:$src2, memop:$src3),
112            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
114              (Int VR128:$src1, VR128:$src2, mem_cpat:$src3))]>, VEX_W, MemOp4;
116            (ins VR128:$src1, memop:$src2, VR128:$src3),
118            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
120              (Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>;
124                (ins VR128:$src1, VR128:$src2, VR128:$src3),
126                "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
133            (ins VR128:$src1, VR128:$src2, VR128:$src3),
135            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
137              (Int128 VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
139            (ins VR128:$src1, VR128:$src2, f128mem:$src3),
141            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
142            [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2,
145            (ins VR128:$src1, f128mem:$src2, VR128:$src3),
147            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
149              (Int128 VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
151            (ins VR256:$src1, VR256:$src2, VR256:$src3),
153            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
155              (Int256 VR256:$src1, VR256:$src2, VR256:$src3))]>, VEX_W, MemOp4;
157            (ins VR256:$src1, VR256:$src2, f256mem:$src3),
159            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
160            [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2,
163            (ins VR256:$src1, f256mem:$src2, VR256:$src3),
165            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
167              (Int256 VR256:$src1, (ld_frag256 addr:$src2), VR256:$src3))]>;
171                (ins VR128:$src1, VR128:$src2, VR128:$src3),
173                "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
175                 (ins VR256:$src1, VR256:$src2, VR256:$src3),
177                 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;