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1//===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes FMA (Fused Multiply-Add) instructions.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// FMA3 - Intel 3 operand Fused Multiply-Add instructions
16//===----------------------------------------------------------------------===//
17
18multiclass fma3p_rm<bits<8> opc, string OpcodeStr> {
19  def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
20           (ins VR128:$src1, VR128:$src2),
21           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
22           []>;
23  def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
24           (ins VR128:$src1, f128mem:$src2),
25           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
26           []>;
27  def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
28           (ins VR256:$src1, VR256:$src2),
29           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
30           []>;
31  def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
32           (ins VR256:$src1, f256mem:$src2),
33           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
34           []>;
35}
36
37multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
38                       string OpcodeStr, string PackTy> {
39  defm r132 : fma3p_rm<opc132, !strconcat(OpcodeStr, !strconcat("132", PackTy))>;
40  defm r213 : fma3p_rm<opc213, !strconcat(OpcodeStr, !strconcat("213", PackTy))>;
41  defm r231 : fma3p_rm<opc231, !strconcat(OpcodeStr, !strconcat("231", PackTy))>;
42}
43
44// Fused Multiply-Add
45let ExeDomain = SSEPackedSingle in {
46  defm VFMADDPS    : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps">;
47  defm VFMSUBPS    : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps">;
48  defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps">;
49  defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps">;
50}
51
52let ExeDomain = SSEPackedDouble in {
53  defm VFMADDPD    : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd">, VEX_W;
54  defm VFMSUBPD    : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd">, VEX_W;
55  defm VFMADDSUBPD : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd">, VEX_W;
56  defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd">, VEX_W;
57}
58
59// Fused Negative Multiply-Add
60let ExeDomain = SSEPackedSingle in {
61  defm VFNMADDPS : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps">;
62  defm VFNMSUBPS : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps">;
63}
64let ExeDomain = SSEPackedDouble in {
65  defm VFNMADDPD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd">, VEX_W;
66  defm VFNMSUBPD : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd">, VEX_W;
67}
68
69multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop> {
70  def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
71           (ins VR128:$src1, VR128:$src2),
72           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
73           []>;
74  def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
75           (ins VR128:$src1, x86memop:$src2),
76           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
77           []>;
78}
79
80multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
81                       string OpcodeStr> {
82  defm SSr132 : fma3s_rm<opc132, !strconcat(OpcodeStr, "132ss"), f32mem>;
83  defm SSr213 : fma3s_rm<opc213, !strconcat(OpcodeStr, "213ss"), f32mem>;
84  defm SSr231 : fma3s_rm<opc231, !strconcat(OpcodeStr, "231ss"), f32mem>;
85  defm SDr132 : fma3s_rm<opc132, !strconcat(OpcodeStr, "132sd"), f64mem>, VEX_W;
86  defm SDr213 : fma3s_rm<opc213, !strconcat(OpcodeStr, "213sd"), f64mem>, VEX_W;
87  defm SDr231 : fma3s_rm<opc231, !strconcat(OpcodeStr, "231sd"), f64mem>, VEX_W;
88}
89
90defm VFMADD : fma3s_forms<0x99, 0xA9, 0xB9, "vfmadd">, VEX_LIG;
91defm VFMSUB : fma3s_forms<0x9B, 0xAB, 0xBB, "vfmsub">, VEX_LIG;
92
93defm VFNMADD : fma3s_forms<0x9D, 0xAD, 0xBD, "vfnmadd">, VEX_LIG;
94defm VFNMSUB : fma3s_forms<0x9F, 0xAF, 0xBF, "vfnmsub">, VEX_LIG;
95
96//===----------------------------------------------------------------------===//
97// FMA4 - AMD 4 operand Fused Multiply-Add instructions
98//===----------------------------------------------------------------------===//
99
100
101multiclass fma4s<bits<8> opc, string OpcodeStr, Operand memop,
102                 ComplexPattern mem_cpat, Intrinsic Int> {
103  def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
104           (ins VR128:$src1, VR128:$src2, VR128:$src3),
105           !strconcat(OpcodeStr,
106           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
107           [(set VR128:$dst,
108             (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
109  def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
110           (ins VR128:$src1, VR128:$src2, memop:$src3),
111           !strconcat(OpcodeStr,
112           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
113           [(set VR128:$dst,
114             (Int VR128:$src1, VR128:$src2, mem_cpat:$src3))]>, VEX_W, MemOp4;
115  def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
116           (ins VR128:$src1, memop:$src2, VR128:$src3),
117           !strconcat(OpcodeStr,
118           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
119           [(set VR128:$dst,
120             (Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>;
121// For disassembler
122let isCodeGenOnly = 1 in
123  def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
124               (ins VR128:$src1, VR128:$src2, VR128:$src3),
125               !strconcat(OpcodeStr,
126               "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
127}
128
129multiclass fma4p<bits<8> opc, string OpcodeStr,
130                 Intrinsic Int128, Intrinsic Int256,
131                 PatFrag ld_frag128, PatFrag ld_frag256> {
132  def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
133           (ins VR128:$src1, VR128:$src2, VR128:$src3),
134           !strconcat(OpcodeStr,
135           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
136           [(set VR128:$dst,
137             (Int128 VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
138  def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
139           (ins VR128:$src1, VR128:$src2, f128mem:$src3),
140           !strconcat(OpcodeStr,
141           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
142           [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2,
143                              (ld_frag128 addr:$src3)))]>, VEX_W, MemOp4;
144  def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
145           (ins VR128:$src1, f128mem:$src2, VR128:$src3),
146           !strconcat(OpcodeStr,
147           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
148           [(set VR128:$dst,
149             (Int128 VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
150  def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
151           (ins VR256:$src1, VR256:$src2, VR256:$src3),
152           !strconcat(OpcodeStr,
153           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
154           [(set VR256:$dst,
155             (Int256 VR256:$src1, VR256:$src2, VR256:$src3))]>, VEX_W, MemOp4;
156  def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
157           (ins VR256:$src1, VR256:$src2, f256mem:$src3),
158           !strconcat(OpcodeStr,
159           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
160           [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2,
161                              (ld_frag256 addr:$src3)))]>, VEX_W, MemOp4;
162  def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
163           (ins VR256:$src1, f256mem:$src2, VR256:$src3),
164           !strconcat(OpcodeStr,
165           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
166           [(set VR256:$dst,
167             (Int256 VR256:$src1, (ld_frag256 addr:$src2), VR256:$src3))]>;
168// For disassembler
169let isCodeGenOnly = 1 in {
170  def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
171               (ins VR128:$src1, VR128:$src2, VR128:$src3),
172               !strconcat(OpcodeStr,
173               "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
174  def rrY_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
175                (ins VR256:$src1, VR256:$src2, VR256:$src3),
176                !strconcat(OpcodeStr,
177                "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
178} // isCodeGenOnly = 1
179}
180
181defm VFMADDSS4    : fma4s<0x6A, "vfmaddss", ssmem, sse_load_f32,
182                          int_x86_fma4_vfmadd_ss>;
183defm VFMADDSD4    : fma4s<0x6B, "vfmaddsd", sdmem, sse_load_f64,
184                          int_x86_fma4_vfmadd_sd>;
185defm VFMADDPS4    : fma4p<0x68, "vfmaddps", int_x86_fma4_vfmadd_ps,
186                          int_x86_fma4_vfmadd_ps_256, memopv4f32, memopv8f32>;
187defm VFMADDPD4    : fma4p<0x69, "vfmaddpd", int_x86_fma4_vfmadd_pd,
188                          int_x86_fma4_vfmadd_pd_256, memopv2f64, memopv4f64>;
189defm VFMSUBSS4    : fma4s<0x6E, "vfmsubss", ssmem, sse_load_f32,
190                          int_x86_fma4_vfmsub_ss>;
191defm VFMSUBSD4    : fma4s<0x6F, "vfmsubsd", sdmem, sse_load_f64,
192                          int_x86_fma4_vfmsub_sd>;
193defm VFMSUBPS4    : fma4p<0x6C, "vfmsubps", int_x86_fma4_vfmsub_ps,
194                          int_x86_fma4_vfmsub_ps_256, memopv4f32, memopv8f32>;
195defm VFMSUBPD4    : fma4p<0x6D, "vfmsubpd", int_x86_fma4_vfmsub_pd,
196                          int_x86_fma4_vfmsub_pd_256, memopv2f64, memopv4f64>;
197defm VFNMADDSS4   : fma4s<0x7A, "vfnmaddss", ssmem, sse_load_f32,
198                          int_x86_fma4_vfnmadd_ss>;
199defm VFNMADDSD4   : fma4s<0x7B, "vfnmaddsd", sdmem, sse_load_f64,
200                          int_x86_fma4_vfnmadd_sd>;
201defm VFNMADDPS4   : fma4p<0x78, "vfnmaddps", int_x86_fma4_vfnmadd_ps,
202                          int_x86_fma4_vfnmadd_ps_256, memopv4f32, memopv8f32>;
203defm VFNMADDPD4   : fma4p<0x79, "vfnmaddpd", int_x86_fma4_vfnmadd_pd,
204                          int_x86_fma4_vfnmadd_pd_256, memopv2f64, memopv4f64>;
205defm VFNMSUBSS4   : fma4s<0x7E, "vfnmsubss", ssmem, sse_load_f32,
206                          int_x86_fma4_vfnmsub_ss>;
207defm VFNMSUBSD4   : fma4s<0x7F, "vfnmsubsd", sdmem, sse_load_f64,
208                          int_x86_fma4_vfnmsub_sd>;
209defm VFNMSUBPS4   : fma4p<0x7C, "vfnmsubps", int_x86_fma4_vfnmsub_ps,
210                          int_x86_fma4_vfnmsub_ps_256, memopv4f32, memopv8f32>;
211defm VFNMSUBPD4   : fma4p<0x7D, "vfnmsubpd", int_x86_fma4_vfnmsub_pd,
212                          int_x86_fma4_vfnmsub_pd_256, memopv2f64, memopv4f64>;
213defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", int_x86_fma4_vfmaddsub_ps,
214                         int_x86_fma4_vfmaddsub_ps_256, memopv4f32, memopv8f32>;
215defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", int_x86_fma4_vfmaddsub_pd,
216                         int_x86_fma4_vfmaddsub_pd_256, memopv2f64, memopv4f64>;
217defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", int_x86_fma4_vfmsubadd_ps,
218                         int_x86_fma4_vfmsubadd_ps_256, memopv4f32, memopv8f32>;
219defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", int_x86_fma4_vfmsubadd_pd,
220                         int_x86_fma4_vfmsubadd_pd_256, memopv2f64, memopv4f64>;
221