| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelDAGToDAG.cpp | 139 bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) { in MatchWrapper()
171 bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) { in MatchAddressBase()
184 bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) { in MatchAddress()
250 MSP430ISelAddressMode AM; in SelectAddr() local
303 ISD::MemIndexedMode AM = LD->getAddressingMode(); in isValidIndexedLoad() local
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| D | MSP430ISelLowering.cpp | 936 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
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| /external/chromium/chrome/common/extensions/docs/examples/extensions/benchmark/jquery/ |
| D | jquery.flot.min.js | 1 …=I!=null?I:1;A.add=function(C,D){for(var E=0;E<C.length;++E){A[C.charAt(E)]+=D}return A.normalize(…
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 176 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, in X86FastEmitLoad()
235 X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM) { in X86FastEmitStore()
281 const X86AddressMode &AM) { in X86FastEmitStore()
337 bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) { in X86SelectAddress()
597 bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) { in X86SelectCallAddress()
700 X86AddressMode AM; in X86SelectStore() local
826 X86AddressMode AM; in X86SelectLoad() local
1433 X86AddressMode AM; in X86VisitIntrinsicCall() local
1440 X86AddressMode AM; in X86VisitIntrinsicCall() local
1748 X86AddressMode AM; in DoSelectCall() local
[all …]
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| D | X86ISelDAGToDAG.cpp | 229 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base, in getAddressOperands()
566 X86ISelAddressMode &AM) { in FoldOffsetIntoAddress()
584 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){ in MatchLoadInAddress()
612 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) { in MatchWrapper()
699 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) { in MatchAddress()
747 X86ISelAddressMode &AM) { in FoldMaskAndShiftToExtract()
790 X86ISelAddressMode &AM) { in FoldMaskedShiftToScaledMask()
857 X86ISelAddressMode &AM) { in FoldMaskAndShiftToScale()
935 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, in MatchAddressRecursively()
1246 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) { in MatchAddressBase()
[all …]
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| D | X86InstrBuilder.h | 123 const X86AddressMode &AM) { in addFullAddress()
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| D | X86InstrInfo.cpp | 2681 X86AddressMode AM; in emitFrameIndexDebugValue() local
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| D | X86ISelLowering.cpp | 11199 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, in isLegalAddressingMode()
12552 X86AddressMode AM; in EmitInstrWithCustomInserter() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 315 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { in getIndexedModeName()
450 const char *AM = getIndexedModeName(LD->getAddressingMode()); in print_details() local
461 const char *AM = getIndexedModeName(ST->getAddressingMode()); in print_details() local
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| D | SelectionDAG.cpp | 488 encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, bool isVolatile, in encodeMemSDNodeFlags()
4134 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad()
4167 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad()
4240 SDValue Offset, ISD::MemIndexedMode AM) { in getIndexedLoad()
4371 SDValue Offset, ISD::MemIndexedMode AM) { in getIndexedStore()
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| D | TargetLowering.cpp | 3221 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, in isLegalAddressingMode()
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| D | DAGCombiner.cpp | 6300 TargetLowering::AddrMode AM; in canFoldInAddressingMode() local
6366 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPreIndexedLoadStore() local
6500 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPostIndexedLoadStore() local
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| /external/llvm/include/llvm/Transforms/Utils/ |
| D | AddrModeMatcher.h | 75 Instruction *MI, ExtAddrMode &AM) in AddressingModeMatcher()
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| /external/llvm/lib/Analysis/ |
| D | TypeBasedAliasAnalysis.cpp | 220 const MDNode *AM = LocA.TBAATag; in alias() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 728 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetReg() local
764 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImmPre() local
784 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImm() local
857 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode3Offset() local
943 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); in SelectAddrMode6Offset() local
1259 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectT2AddrModeImm8Offset() local
1332 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectARMIndexedLoad() local
1405 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectT2IndexedLoad() local
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| D | ARMISelLowering.cpp | 8616 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM, in isLegalT2ScaledAddressingMode()
8651 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, in isLegalAddressingMode()
8822 ISD::MemIndexedMode &AM, in getPreIndexedAddressParts()
8861 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
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| /external/icu4c/i18n/unicode/ |
| D | calendar.h | 257 AM, enumerator
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 626 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
1419 bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM, in isLegalAddressingMode()
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| D | HexagonISelDAGToDAG.cpp | 581 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectLoad() local
720 ISD::MemIndexedMode AM = ST->getAddressingMode(); in SelectStore() local
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| /external/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 226 TargetLowering::AddrMode AM; member
1261 static bool isLegalUse(const TargetLowering::AddrMode &AM, in isLegalUse()
1318 static bool isLegalUse(TargetLowering::AddrMode AM, in isLegalUse()
1349 TargetLowering::AddrMode AM; in isAlwaysFoldable() local
1387 TargetLowering::AddrMode AM; in isAlwaysFoldable() local
1978 TargetLowering::AddrMode AM; in OptimizeLoopTermCond() local
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| /external/llvm/tools/llvm-stress/ |
| D | llvm-stress.cpp | 639 AllocaModifier AM(BB, &PT, &R); AM.ActN(5); // Throw in a few allocas in FillFunction() local
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1564 XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, in isLegalAddressingMode()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 1085 ISD::MemIndexedMode &AM, in getPreIndexedAddressParts()
5706 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, in isLegalAddressingMode()
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 3243 SPUTargetLowering::isLegalAddressingMode(const AddrMode &AM, in isLegalAddressingMode() argument
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| /external/llvm/utils/TableGen/ |
| D | CodeGenDAGPatterns.cpp | 706 const ComplexPattern *AM = P->getComplexPatternInfo(CGP); in getPatternSize() local
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