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Searched defs:SDValue (Results 1 – 14 of 14) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DSelectionDAGNodes.h94 SDValue() : Node(0), ResNo(0) {} in SDValue() function
95 SDValue(SDNode *node, unsigned resno) : Node(node), ResNo(resno) {} in SDValue() function
DAnalysis.h30 class SDValue; variable
DSelectionDAGISel.h26 class SDValue; variable
256 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) { in CheckComplexPattern()
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp68 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { in EmitCopyFromReg()
190 DenseMap<SDValue, unsigned> &VRBaseMap) { in CreateVirtualRegisters()
247 DenseMap<SDValue, unsigned> &VRBaseMap) { in getVR()
276 DenseMap<SDValue, unsigned> &VRBaseMap, in AddRegisterOperand()
342 DenseMap<SDValue, unsigned> &VRBaseMap, in AddOperand()
429 DenseMap<SDValue, unsigned> &VRBaseMap, in EmitSubregNode()
546 DenseMap<SDValue, unsigned> &VRBaseMap) { in EmitCopyToRegClassNode()
565 DenseMap<SDValue, unsigned> &VRBaseMap, in EmitRegSequence()
609 DenseMap<SDValue, unsigned> &VRBaseMap) { in EmitDbgValue()
665 DenseMap<SDValue, unsigned> &VRBaseMap) { in EmitMachineNode()
[all …]
DInstrEmitter.h122 DenseMap<SDValue, unsigned> &VRBaseMap) { in EmitNode()
DScheduleDAGSDNodes.cpp669 DenseMap<SDValue, unsigned> &VRBaseMap, in ProcessSDDbgValues()
699 DenseMap<SDValue, unsigned> &VRBaseMap, in ProcessSourceNode()
DLegalizeVectorTypes.cpp2274 SmallVector<SDValue, 16>& LdOps, in BuildVectorFromScalar()
2301 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain, in GenWidenVectorLoads()
2457 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain, in GenWidenVectorExtLoads()
2505 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain, in GenWidenVectorStores()
2574 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain, in GenWidenVectorTruncStores()
DSelectionDAGISel.cpp1985 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { in CheckSame()
2098 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { in IsPredicateKnownToFail()
DDAGCombiner.cpp8651 SmallVector<SDValue, 8> &Aliases) { in GatherAllAliases()
/external/llvm/lib/Target/PTX/
DPTXInstrInfo.h27 class SDValue; variable
/external/llvm/include/llvm/Target/
DTargetLowering.h747 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/, in getPreIndexedAddressParts() argument
758 SDValue &/*Base*/, SDValue &/*Offset*/, in getPostIndexedAddressParts() argument
948 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const { in IsDesirableToPromoteOp() argument
1192 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, in LowerFormalArguments() argument
1196 SmallVectorImpl<SDValue> &/*InVals*/) const { in LowerFormalArguments()
1235 LowerCall(SDValue /*Chain*/, SDValue /*Callee*/, in LowerCall() argument
1239 const SmallVectorImpl<SDValue> &/*OutVals*/, in LowerCall()
1268 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, in LowerReturn() argument
1271 const SmallVectorImpl<SDValue> &/*OutVals*/, in LowerReturn()
1338 SmallVectorImpl<SDValue> &/*Results*/, in ReplaceNodeResults()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp2155 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass, in WriteByValArg() argument
2156 SmallVector<SDValue, 8>& MemOpChains, int& LastFI, in WriteByValArg()
2246 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass, in PassByValArg64() argument
2247 SmallVector<SDValue, 8>& MemOpChains, int& LastFI, in PassByValArg64()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp2393 SmallVector<SDValue, 8> &MemOpChains, in StoreTailCallArgumentsToStackSlot()
2516 bool isVector, SmallVector<SDValue, 8> &MemOpChains, in LowerMemOpCallTo()
2568 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, in PrepareCall() argument
2569 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys, in PrepareCall()
2767 SmallVector<std::pair<unsigned, SDValue>, 8> in FinishCall() argument
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp1265 SmallVector<SDValue, 8> &MemOpChains, in PassF64ArgInRegs()