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Searched refs:ANY_EXTEND (Results 1 – 25 of 27) sorted by relevance

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/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp95 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; in PromoteIntegerResult()
224 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
231 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
245 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
259 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
277 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), in PromoteIntRes_BUILD_PAIR()
404 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); in PromoteIntRes_INT_EXTEND()
759 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; in PromoteIntegerOperand()
845 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); in PromoteIntOp_ANY_EXTEND()
1021 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); in PromoteIntOp_SIGN_EXTEND()
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DDAGCombiner.cpp753 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) in PromoteOperand()
755 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); in PromoteOperand()
1126 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); in visit()
1199 case ISD::ANY_EXTEND: in combine()
2305 (N0.getOpcode() == ISD::ANY_EXTEND && in SimplifyBinOpWithSameOpcodeHands()
2441 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitAND()
2646 (N0.getOpcode() == ISD::ANY_EXTEND && in visitAND()
2648 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; in visitAND()
3232 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND in MatchRotate()
3236 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND in MatchRotate()
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DTargetLowering.cpp1013 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; in GetReturnInfo()
1024 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { in GetReturnInfo()
1476 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { in SimplifyDemandedBits()
1490 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), in SimplifyDemandedBits()
1664 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, in SimplifyDemandedBits()
1686 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, in SimplifyDemandedBits()
1718 case ISD::ANY_EXTEND: { in SimplifyDemandedBits()
2237 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), in SimplifySetCC()
DLegalizeVectorTypes.cpp67 case ISD::ANY_EXTEND: in ScalarizeVectorResult()
398 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), in ScalarizeVecOp_EXTRACT_VECTOR_ELT()
477 case ISD::ANY_EXTEND: in SplitVectorResult()
1003 case ISD::ANY_EXTEND: in SplitVectorOperand()
1293 case ISD::ANY_EXTEND: in WidenVectorResult()
2059 case ISD::ANY_EXTEND: in WidenVectorOperand()
DSelectionDAGDumper.cpp215 case ISD::ANY_EXTEND: return "any_extend"; in getOperationName()
DLegalizeVectorOps.cpp198 case ISD::ANY_EXTEND: in LegalizeOp()
DSelectionDAGBuilder.cpp151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); in getCopyFromParts()
193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); in getCopyFromParts()
289 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), in getCopyFromPartsVector()
307 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), in getCopyFromPartsVector()
327 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { in getCopyToParts()
484 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), in getCopyToPartsVector()
494 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), in getCopyToPartsVector()
1202 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; in visitRet()
1210 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) in visitRet()
6425 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; in LowerCallTo()
DSelectionDAG.cpp904 getNode(ISD::ANY_EXTEND, DL, VT, Op) : in getAnyExtOrTrunc()
1926 case ISD::ANY_EXTEND: { in ComputeMaskedBits()
2387 case ISD::ANY_EXTEND: in getNode()
2514 case ISD::ANY_EXTEND: in getNode()
2526 OpOpcode == ISD::ANY_EXTEND) in getNode()
2552 OpOpcode == ISD::ANY_EXTEND) { in getNode()
2869 Elt = getNode(ISD::ANY_EXTEND, DL, VT, Elt); in getNode()
DLegalizeTypes.cpp1010 Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi); in JoinIntegers()
DLegalizeDAG.cpp1126 ISD::FP_EXTEND : ISD::ANY_EXTEND); in LegalizeOp()
3305 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); in ExpandNode()
3577 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
3594 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
DLegalizeFloatTypes.cpp199 SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h364 ANY_EXTEND, enumerator
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp479 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
868 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val), in LowerSIGN_EXTEND()
/external/llvm/lib/Target/CellSPU/
DSPUISelLowering.cpp468 setTargetDAGCombine(ISD::ANY_EXTEND); in SPUTargetLowering()
741 unsigned NewOpc = ISD::ANY_EXTEND; in LowerLOAD()
2965 case ISD::ANY_EXTEND: { in PerformDAGCombine()
3038 case ISD::ANY_EXTEND: in PerformDAGCombine()
DSPUISelDAGToDAG.cpp640 } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND) in Select()
/external/llvm/include/llvm/Target/
DTargetLowering.h112 return ISD::ANY_EXTEND; in getExtendForContent()
DTargetSelectionDAG.td359 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
/external/llvm/lib/Target/MBlaze/
DMBlazeISelLowering.cpp736 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); in LowerCall()
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp888 if (X.getOpcode() == ISD::ANY_EXTEND) { in FoldMaskAndShiftToScale()
1124 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND || in MatchAddressRecursively()
DX86ISelLowering.cpp766 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); in X86TargetLowering()
2241 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); in LowerCall()
6876 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); in LowerINSERT_VECTOR_ELT_SSE4()
6942 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); in LowerINSERT_VECTOR_ELT()
6976 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); in LowerSCALAR_TO_VECTOR()
8279 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); in LowerToBT()
8284 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); in LowerToBT()
13776 ((N00.getOpcode() == ISD::ANY_EXTEND || in PerformSHLCombine()
13974 case ISD::ANY_EXTEND: in CMPEQCombine()
15148 case ISD::ANY_EXTEND: in isTypeDesirableForOp()
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DX86FastISel.cpp1719 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), in DoSelectCall()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp461 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp426 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp949 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp552 setTargetDAGCombine(ISD::ANY_EXTEND); in ARMTargetLowering()
1362 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
8245 case ISD::ANY_EXTEND: in PerformExtendCombine()
8432 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()

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