| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 57 AssertSext, AssertZext, enumerator
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
163 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(), in PromoteIntRes_AssertZext()
371 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, in PromoteIntRes_FP_TO_XINT()
381 return DAG.getNode(ISD::AssertZext, dl, in PromoteIntRes_FP32_TO_FP16()
1104 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; in ExpandIntegerResult()
1683 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, in ExpandIntRes_AssertZext()
1687 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertZext()
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| D | SelectionDAGDumper.cpp | 80 case ISD::AssertZext: return "AssertZext"; in getOperationName()
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| D | SelectionDAGBuilder.cpp | 718 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
4387 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ in getTruncatedArgReg()
6506 AssertOp = ISD::AssertZext; in LowerCallTo()
6733 AssertOp = ISD::AssertZext; in LowerArguments()
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| D | SelectionDAG.cpp | 1947 case ISD::AssertZext: { in ComputeMaskedBits()
2099 case ISD::AssertZext: in ComputeNumSignBits()
2803 case ISD::AssertZext: { in getNode()
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| D | SelectionDAGISel.cpp | 2202 case ISD::AssertZext: in SelectCodeCommon()
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| D | TargetLowering.cpp | 1788 case ISD::AssertZext: { in SimplifyDemandedBits()
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| D | DAGCombiner.cpp | 742 case ISD::AssertZext: in PromoteOperand()
743 return DAG.getNode(ISD::AssertZext, dl, PVT, in PromoteOperand()
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| D | LegalizeDAG.cpp | 1003 Result = DAG.getNode(ISD::AssertZext, dl, in LegalizeOp()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 922 Opcode = ISD::AssertZext; in LowerFormalArguments()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 345 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
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| /external/llvm/lib/Target/X86/ |
| D | README-SSE.txt | 497 SSE4 extract-to-mem ops aren't being pattern matched because of the AssertZext
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| D | X86ISelLowering.cpp | 1880 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
6715 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, in LowerEXTRACT_VECTOR_ELT_SSE4()
6730 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, in LowerEXTRACT_VECTOR_ELT_SSE4()
6812 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, in LowerEXTRACT_VECTOR_ELT()
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| D | X86InstrSSE.td | 5909 // There's an AssertZext in the way of writing the store pattern
5932 // There's an AssertZext in the way of writing the store pattern
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 2661 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
8392 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
8395 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
8398 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2805 Opcode = ISD::AssertZext; in LowerFormalArguments()
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 875 && (theValue.getOpcode() == ISD::AssertZext in LowerSTORE()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 2090 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, in LowerFormalArguments_Darwin()
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