| /external/llvm/include/llvm/Target/ |
| D | TargetOpcodes.h | 52 IMPLICIT_DEF = 8, enumerator
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| D | TargetInstrInfo.h | 67 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
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| /external/llvm/test/CodeGen/X86/ |
| D | insertelement-copytoregs.ll | 1 ; RUN: llc < %s -march=x86-64 | grep -v IMPLICIT_DEF
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| D | fp-stack-O0-crash.ll | 33 ; This produces a FP0 = IMPLICIT_DEF instruction.
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| D | 2008-01-16-InvalidDAGCombineXform.ll | 1 ; RUN: llc < %s -march=x86 | not grep IMPLICIT_DEF
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | 2006-10-13-Miscompile.ll | 1 ; RUN: llc < %s -march=ppc32 | not grep IMPLICIT_DEF
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| /external/llvm/lib/CodeGen/ |
| D | ProcessImplicitDefs.cpp | 155 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); in runOnMachineFunction()
253 RMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); in runOnMachineFunction()
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| D | MachineSSAUpdater.cpp | 149 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetValueInMiddleOfBlock()
302 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetUndefVal()
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| D | PHIElimination.cpp | 219 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg); in LowerAtomicPHINode()
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| D | TwoAddressInstructionPass.cpp | 1925 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); in EliminateRegSequences()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 268 case TargetOpcode::IMPLICIT_DEF: in isResourceAvailable()
308 case TargetOpcode::IMPLICIT_DEF: in reserveResources()
555 if (N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { in initNumRegDefsLeft()
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| D | InstrEmitter.cpp | 191 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && in CreateVirtualRegisters()
249 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { in getVR()
259 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
688 if (Opc == TargetOpcode::IMPLICIT_DEF) in EmitMachineNode()
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| D | ScheduleDAGSDNodes.cpp | 82 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)) in newSUnit()
506 if (POpc == TargetOpcode::IMPLICIT_DEF) { in InitNodeNumDefs()
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| D | ScheduleDAGRRList.cpp | 2082 Opc == TargetOpcode::IMPLICIT_DEF) in unscheduledNode()
2105 if (POpc == TargetOpcode::IMPLICIT_DEF) in unscheduledNode()
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| D | FastISel.cpp | 215 TII.get(TargetOpcode::IMPLICIT_DEF), Reg); in materializeRegForValue()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrSSE.td | 272 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
274 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
276 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
278 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
280 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
282 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
286 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
288 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
291 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
293 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
[all …]
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| D | X86CodeEmitter.cpp | 756 case TargetOpcode::IMPLICIT_DEF: in emitInstruction()
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| D | X86ISelDAGToDAG.cpp | 1616 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, in SelectAtomicLoadAdd()
1778 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, in SelectAtomicLoadArith()
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| D | X86FloatingPoint.cpp | 1396 case TargetOpcode::IMPLICIT_DEF: { in handleSpecialFP()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCodeEmitter.cpp | 124 case TargetOpcode::IMPLICIT_DEF: in emitBasicBlock()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 301 case TargetOpcode::IMPLICIT_DEF: in GetInstSizeInBytes()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 5042 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5044 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
5046 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5049 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5051 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5053 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5056 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
5057 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5060 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
5061 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
[all …]
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| D | ARMISelDAGToDAG.cpp | 1685 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0); in SelectVLD()
1795 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) in SelectVST()
1843 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) in SelectVST()
1961 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) in SelectVLDSTLane()
2097 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) in SelectVTBL()
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| D | ARMCodeEmitter.cpp | 942 case TargetOpcode::IMPLICIT_DEF: in emitPseudoInstruction()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 604 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
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