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Searched refs:R10 (Results 1 – 25 of 53) sorted by relevance

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/external/llvm/test/CodeGen/Mips/
Datomic.ll89 ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
90 ; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
92 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
97 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
120 ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
121 ; CHECK: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
123 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
128 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
151 ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
152 ; CHECK: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
[all …]
/external/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.cpp303 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, in getRawAllocationOrder()
310 ARM::R8, ARM::R10 in getRawAllocationOrder()
315 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, in getRawAllocationOrder()
322 ARM::R8, ARM::R10 in getRawAllocationOrder()
328 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, in getRawAllocationOrder()
333 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, in getRawAllocationOrder()
339 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, in getRawAllocationOrder()
346 ARM::R10 in getRawAllocationOrder()
351 ARM::R0, ARM::R2, ARM::R4, ARM::R10, in getRawAllocationOrder()
358 ARM::R10 in getRawAllocationOrder()
[all …]
DARMBaseRegisterInfo.h45 case R8: case R9: case R10: case R11: in isARMArea1Register()
56 case R8: case R9: case R10: case R11: in isARMArea2Register()
/external/llvm/lib/Target/XCore/
DXCoreFrameLowering.cpp172 storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl, TII); in emitPrologue()
174 MBB.addLiveIn(XCore::R10); in emitPrologue()
179 MachineLocation CSSrc(XCore::R10); in emitPrologue()
183 unsigned FramePtr = XCore::R10; in emitPrologue()
224 unsigned FramePtr = XCore::R10; in emitEpilogue()
250 loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl, TII); in emitEpilogue()
DXCoreRegisterInfo.td36 def R10 : Ri<10, "r10">, DwarfRegNum<[10]>;
51 R4, R5, R6, R7, R8, R9, R10)>;
DXCoreRegisterInfo.cpp66 XCore::R8, XCore::R9, XCore::R10, XCore::LR, in getCalleeSavedRegs()
81 Reserved.set(XCore::R10); in getReservedRegs()
312 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP; in getFrameRegister()
/external/llvm/lib/Target/MBlaze/MCTargetDesc/
DMBlazeBaseInfo.h115 case MBlaze::R10 : return 10; in getMBlazeRegisterNumbering()
179 case 10 : return MBlaze::R10; in getMBlazeRegisterFromNumbering()
/external/llvm/lib/Target/CellSPU/
DSPUCallingConv.td21 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
38 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
/external/valgrind/main/VEX/orig_ppc32/
Dreturn0.orig242 1: PUTL t0, R10
252 7: GETL R10, t6
298 39: GETL R10, t28
327 60: PUTL t46, R10
436 3: GETL R10, t4
441 6: GETL R10, t6
443 8: PUTL t6, R10
525 12: GETL R10, t10
530 15: GETL R10, t12
532 17: PUTL t12, R10
[all …]
Ddate.orig242 1: PUTL t0, R10
252 7: GETL R10, t6
298 39: GETL R10, t28
327 60: PUTL t46, R10
436 3: GETL R10, t4
441 6: GETL R10, t6
443 8: PUTL t6, R10
525 12: GETL R10, t10
530 15: GETL R10, t12
532 17: PUTL t12, R10
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td74 def R10 : Ri<10, "r10">, DwarfRegNum<[10]>;
108 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
146 R10, R11, R29, R30, R31)> {
DHexagonRegisterInfo.h36 #define HEXAGON_RESERVED_REG_1 Hexagon::R10
/external/kernel-headers/original/asm-x86/
Dptrace-abi.h36 #define R10 56 macro
/external/llvm/lib/Target/X86/
DX86RegisterInfo.cpp99 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: in getSEHRegNum()
308 X86::R8, X86::R9, X86::R10, X86::R11, in getReservedRegs()
575 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegister()
612 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegister()
648 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegister()
700 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegister()
701 return X86::R10; in getX86SubSuperRegister()
DX86InstrControl.td238 // __chkstk(MSVC): clobber R10, R11 and EFLAGS.
239 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
240 let Defs = [RAX, R10, R11, RSP, EFLAGS],
DX86CallingConv.td143 // The 'nest' parameter, if any, is passed in R10.
144 CCIfNest<CCAssignToReg<[R10]>>,
195 // The 'nest' parameter, if any, is passed in R10.
196 CCIfNest<CCAssignToReg<[R10]>>,
DX86FrameLowering.cpp104 X86::R8, X86::R9, X86::R10, X86::R11, 0 in findDeadCallerSavedReg()
1392 allocMBB->addLiveIn(X86::R10); in adjustForSegmentedStacks()
1503 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10); in adjustForSegmentedStacks()
1505 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10) in adjustForSegmentedStacks()
1509 MF.getRegInfo().setPhysRegUsed(X86::R10); in adjustForSegmentedStacks()
/external/llvm/lib/Target/PowerPC/
DPPCCallingConv.td21 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
38 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
71 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCBaseInfo.h41 case R10: case X10: case F10: case V10: case CR2EQ: return 10; in getPPCRegisterNumbering()
/external/valgrind/main/coregrind/m_sigframe/
Dsigframe-arm-linux.c148 SC2(r10,R10); in synth_ucontext()
322 REST(r10,R10); in VG_()
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h170 ENTRY(R10) \
188 ENTRY(R10) \
/external/valgrind/main/VEX/auxprogs/
Dgenoffsets.c110 GENOFFSET(AMD64,amd64,R10); in foo()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp233 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: in getX86RegNum()
310 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: in InitLLVM2SEHRegisterMapping()
DX86BaseInfo.h552 case X86::R8: case X86::R9: case X86::R10: case X86::R11: in isX86_64ExtendedReg()
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMBaseInfo.h165 case R10: case S10: case D10: case Q10: return 10; in getARMRegisterNumbering()

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