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1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
12 // on X86.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "X86RegisterInfo.h"
17 #include "X86.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/CommandLine.h"
41 
42 #define GET_REGINFO_TARGET_DESC
43 #include "X86GenRegisterInfo.inc"
44 
45 using namespace llvm;
46 
47 cl::opt<bool>
48 ForceStackAlign("force-align-stack",
49                  cl::desc("Force align the stack to the minimum alignment"
50                            " needed for the function."),
51                  cl::init(false), cl::Hidden);
52 
X86RegisterInfo(X86TargetMachine & tm,const TargetInstrInfo & tii)53 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
54                                  const TargetInstrInfo &tii)
55   : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit()
56                          ? X86::RIP : X86::EIP,
57                        X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
58                        X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)),
59                        TM(tm), TII(tii) {
60   X86_MC::InitLLVM2SEHRegisterMapping(this);
61 
62   // Cache some information.
63   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
64   Is64Bit = Subtarget->is64Bit();
65   IsWin64 = Subtarget->isTargetWin64();
66 
67   if (Is64Bit) {
68     SlotSize = 8;
69     StackPtr = X86::RSP;
70     FramePtr = X86::RBP;
71   } else {
72     SlotSize = 4;
73     StackPtr = X86::ESP;
74     FramePtr = X86::EBP;
75   }
76 }
77 
78 /// getCompactUnwindRegNum - This function maps the register to the number for
79 /// compact unwind encoding. Return -1 if the register isn't valid.
getCompactUnwindRegNum(unsigned RegNum,bool isEH) const80 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
81   switch (getLLVMRegNum(RegNum, isEH)) {
82   case X86::EBX: case X86::RBX: return 1;
83   case X86::ECX: case X86::R12: return 2;
84   case X86::EDX: case X86::R13: return 3;
85   case X86::EDI: case X86::R14: return 4;
86   case X86::ESI: case X86::R15: return 5;
87   case X86::EBP: case X86::RBP: return 6;
88   }
89 
90   return -1;
91 }
92 
93 int
getSEHRegNum(unsigned i) const94 X86RegisterInfo::getSEHRegNum(unsigned i) const {
95   int reg = X86_MC::getX86RegNum(i);
96   switch (i) {
97   case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
98   case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
99   case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
100   case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
101   case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
102   case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
103   case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
104   case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
105   case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
106   case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
107   case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
108   case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
109     reg += 8;
110   }
111   return reg;
112 }
113 
114 const TargetRegisterClass *
getSubClassWithSubReg(const TargetRegisterClass * RC,unsigned Idx) const115 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
116                                        unsigned Idx) const {
117   // The sub_8bit sub-register index is more constrained in 32-bit mode.
118   // It behaves just like the sub_8bit_hi index.
119   if (!Is64Bit && Idx == X86::sub_8bit)
120     Idx = X86::sub_8bit_hi;
121 
122   // Forward to TableGen's default version.
123   return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
124 }
125 
126 const TargetRegisterClass *
getMatchingSuperRegClass(const TargetRegisterClass * A,const TargetRegisterClass * B,unsigned SubIdx) const127 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
128                                           const TargetRegisterClass *B,
129                                           unsigned SubIdx) const {
130   // The sub_8bit sub-register index is more constrained in 32-bit mode.
131   if (!Is64Bit && SubIdx == X86::sub_8bit) {
132     A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
133     if (!A)
134       return 0;
135   }
136   return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
137 }
138 
139 const TargetRegisterClass*
getLargestLegalSuperClass(const TargetRegisterClass * RC) const140 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
141   // Don't allow super-classes of GR8_NOREX.  This class is only used after
142   // extrating sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
143   // to the full GR8 register class in 64-bit mode, so we cannot allow the
144   // reigster class inflation.
145   //
146   // The GR8_NOREX class is always used in a way that won't be constrained to a
147   // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
148   // full GR8 class.
149   if (RC == X86::GR8_NOREXRegisterClass)
150     return RC;
151 
152   const TargetRegisterClass *Super = RC;
153   TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
154   do {
155     switch (Super->getID()) {
156     case X86::GR8RegClassID:
157     case X86::GR16RegClassID:
158     case X86::GR32RegClassID:
159     case X86::GR64RegClassID:
160     case X86::FR32RegClassID:
161     case X86::FR64RegClassID:
162     case X86::RFP32RegClassID:
163     case X86::RFP64RegClassID:
164     case X86::RFP80RegClassID:
165     case X86::VR128RegClassID:
166     case X86::VR256RegClassID:
167       // Don't return a super-class that would shrink the spill size.
168       // That can happen with the vector and float classes.
169       if (Super->getSize() == RC->getSize())
170         return Super;
171     }
172     Super = *I++;
173   } while (Super);
174   return RC;
175 }
176 
177 const TargetRegisterClass *
getPointerRegClass(unsigned Kind) const178 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
179   switch (Kind) {
180   default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
181   case 0: // Normal GPRs.
182     if (TM.getSubtarget<X86Subtarget>().is64Bit())
183       return &X86::GR64RegClass;
184     return &X86::GR32RegClass;
185   case 1: // Normal GPRs except the stack pointer (for encoding reasons).
186     if (TM.getSubtarget<X86Subtarget>().is64Bit())
187       return &X86::GR64_NOSPRegClass;
188     return &X86::GR32_NOSPRegClass;
189   case 2: // Available for tailcall (not callee-saved GPRs).
190     if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
191       return &X86::GR64_TCW64RegClass;
192     if (TM.getSubtarget<X86Subtarget>().is64Bit())
193       return &X86::GR64_TCRegClass;
194     return &X86::GR32_TCRegClass;
195   }
196 }
197 
198 const TargetRegisterClass *
getCrossCopyRegClass(const TargetRegisterClass * RC) const199 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
200   if (RC == &X86::CCRRegClass) {
201     if (Is64Bit)
202       return &X86::GR64RegClass;
203     else
204       return &X86::GR32RegClass;
205   }
206   return RC;
207 }
208 
209 unsigned
getRegPressureLimit(const TargetRegisterClass * RC,MachineFunction & MF) const210 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
211                                      MachineFunction &MF) const {
212   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
213 
214   unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
215   switch (RC->getID()) {
216   default:
217     return 0;
218   case X86::GR32RegClassID:
219     return 4 - FPDiff;
220   case X86::GR64RegClassID:
221     return 12 - FPDiff;
222   case X86::VR128RegClassID:
223     return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
224   case X86::VR64RegClassID:
225     return 4;
226   }
227 }
228 
229 const uint16_t *
getCalleeSavedRegs(const MachineFunction * MF) const230 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
231   bool callsEHReturn = false;
232   bool ghcCall = false;
233 
234   if (MF) {
235     callsEHReturn = MF->getMMI().callsEHReturn();
236     const Function *F = MF->getFunction();
237     ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
238   }
239 
240   if (ghcCall)
241     return CSR_Ghc_SaveList;
242   if (Is64Bit) {
243     if (IsWin64)
244       return CSR_Win64_SaveList;
245     if (callsEHReturn)
246       return CSR_64EHRet_SaveList;
247     return CSR_64_SaveList;
248   }
249   if (callsEHReturn)
250     return CSR_32EHRet_SaveList;
251   return CSR_32_SaveList;
252 }
253 
254 const uint32_t*
getCallPreservedMask(CallingConv::ID CC) const255 X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
256   if (CC == CallingConv::GHC)
257     return CSR_Ghc_RegMask;
258   if (!Is64Bit)
259     return CSR_32_RegMask;
260   if (IsWin64)
261     return CSR_Win64_RegMask;
262   return CSR_64_RegMask;
263 }
264 
getReservedRegs(const MachineFunction & MF) const265 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
266   BitVector Reserved(getNumRegs());
267   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
268 
269   // Set the stack-pointer register and its aliases as reserved.
270   Reserved.set(X86::RSP);
271   Reserved.set(X86::ESP);
272   Reserved.set(X86::SP);
273   Reserved.set(X86::SPL);
274 
275   // Set the instruction pointer register and its aliases as reserved.
276   Reserved.set(X86::RIP);
277   Reserved.set(X86::EIP);
278   Reserved.set(X86::IP);
279 
280   // Set the frame-pointer register and its aliases as reserved if needed.
281   if (TFI->hasFP(MF)) {
282     Reserved.set(X86::RBP);
283     Reserved.set(X86::EBP);
284     Reserved.set(X86::BP);
285     Reserved.set(X86::BPL);
286   }
287 
288   // Mark the segment registers as reserved.
289   Reserved.set(X86::CS);
290   Reserved.set(X86::SS);
291   Reserved.set(X86::DS);
292   Reserved.set(X86::ES);
293   Reserved.set(X86::FS);
294   Reserved.set(X86::GS);
295 
296   // Reserve the registers that only exist in 64-bit mode.
297   if (!Is64Bit) {
298     // These 8-bit registers are part of the x86-64 extension even though their
299     // super-registers are old 32-bits.
300     Reserved.set(X86::SIL);
301     Reserved.set(X86::DIL);
302     Reserved.set(X86::BPL);
303     Reserved.set(X86::SPL);
304 
305     for (unsigned n = 0; n != 8; ++n) {
306       // R8, R9, ...
307       static const uint16_t GPR64[] = {
308         X86::R8,  X86::R9,  X86::R10, X86::R11,
309         X86::R12, X86::R13, X86::R14, X86::R15
310       };
311       for (const uint16_t *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; ++AI)
312         Reserved.set(Reg);
313 
314       // XMM8, XMM9, ...
315       assert(X86::XMM15 == X86::XMM8+7);
316       for (const uint16_t *AI = getOverlaps(X86::XMM8 + n); unsigned Reg = *AI;
317            ++AI)
318         Reserved.set(Reg);
319     }
320   }
321 
322   return Reserved;
323 }
324 
325 //===----------------------------------------------------------------------===//
326 // Stack Frame Processing methods
327 //===----------------------------------------------------------------------===//
328 
canRealignStack(const MachineFunction & MF) const329 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
330   const MachineFrameInfo *MFI = MF.getFrameInfo();
331   return (MF.getTarget().Options.RealignStack &&
332           !MFI->hasVarSizedObjects());
333 }
334 
needsStackRealignment(const MachineFunction & MF) const335 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
336   const MachineFrameInfo *MFI = MF.getFrameInfo();
337   const Function *F = MF.getFunction();
338   unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
339   bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
340                                F->hasFnAttr(Attribute::StackAlignment));
341 
342   // FIXME: Currently we don't support stack realignment for functions with
343   //        variable-sized allocas.
344   // FIXME: It's more complicated than this...
345   if (0 && requiresRealignment && MFI->hasVarSizedObjects())
346     report_fatal_error(
347       "Stack realignment in presence of dynamic allocas is not supported");
348 
349   // If we've requested that we force align the stack do so now.
350   if (ForceStackAlign)
351     return canRealignStack(MF);
352 
353   return requiresRealignment && canRealignStack(MF);
354 }
355 
hasReservedSpillSlot(const MachineFunction & MF,unsigned Reg,int & FrameIdx) const356 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
357                                            unsigned Reg, int &FrameIdx) const {
358   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
359 
360   if (Reg == FramePtr && TFI->hasFP(MF)) {
361     FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
362     return true;
363   }
364   return false;
365 }
366 
getSUBriOpcode(unsigned is64Bit,int64_t Imm)367 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
368   if (is64Bit) {
369     if (isInt<8>(Imm))
370       return X86::SUB64ri8;
371     return X86::SUB64ri32;
372   } else {
373     if (isInt<8>(Imm))
374       return X86::SUB32ri8;
375     return X86::SUB32ri;
376   }
377 }
378 
getADDriOpcode(unsigned is64Bit,int64_t Imm)379 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
380   if (is64Bit) {
381     if (isInt<8>(Imm))
382       return X86::ADD64ri8;
383     return X86::ADD64ri32;
384   } else {
385     if (isInt<8>(Imm))
386       return X86::ADD32ri8;
387     return X86::ADD32ri;
388   }
389 }
390 
391 void X86RegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator I) const392 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
393                               MachineBasicBlock::iterator I) const {
394   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
395   bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
396   int Opcode = I->getOpcode();
397   bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
398   DebugLoc DL = I->getDebugLoc();
399   uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
400   uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
401   I = MBB.erase(I);
402 
403   if (!reseveCallFrame) {
404     // If the stack pointer can be changed after prologue, turn the
405     // adjcallstackup instruction into a 'sub ESP, <amt>' and the
406     // adjcallstackdown instruction into 'add ESP, <amt>'
407     // TODO: consider using push / pop instead of sub + store / add
408     if (Amount == 0)
409       return;
410 
411     // We need to keep the stack aligned properly.  To do this, we round the
412     // amount of space needed for the outgoing arguments up to the next
413     // alignment boundary.
414     unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
415     Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
416 
417     MachineInstr *New = 0;
418     if (Opcode == TII.getCallFrameSetupOpcode()) {
419       New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
420                     StackPtr)
421         .addReg(StackPtr)
422         .addImm(Amount);
423     } else {
424       assert(Opcode == TII.getCallFrameDestroyOpcode());
425 
426       // Factor out the amount the callee already popped.
427       Amount -= CalleeAmt;
428 
429       if (Amount) {
430         unsigned Opc = getADDriOpcode(Is64Bit, Amount);
431         New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
432           .addReg(StackPtr).addImm(Amount);
433       }
434     }
435 
436     if (New) {
437       // The EFLAGS implicit def is dead.
438       New->getOperand(3).setIsDead();
439 
440       // Replace the pseudo instruction with a new instruction.
441       MBB.insert(I, New);
442     }
443 
444     return;
445   }
446 
447   if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
448     // If we are performing frame pointer elimination and if the callee pops
449     // something off the stack pointer, add it back.  We do this until we have
450     // more advanced stack pointer tracking ability.
451     unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
452     MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
453       .addReg(StackPtr).addImm(CalleeAmt);
454 
455     // The EFLAGS implicit def is dead.
456     New->getOperand(3).setIsDead();
457 
458     // We are not tracking the stack pointer adjustment by the callee, so make
459     // sure we restore the stack pointer immediately after the call, there may
460     // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
461     MachineBasicBlock::iterator B = MBB.begin();
462     while (I != B && !llvm::prior(I)->isCall())
463       --I;
464     MBB.insert(I, New);
465   }
466 }
467 
468 void
eliminateFrameIndex(MachineBasicBlock::iterator II,int SPAdj,RegScavenger * RS) const469 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
470                                      int SPAdj, RegScavenger *RS) const{
471   assert(SPAdj == 0 && "Unexpected");
472 
473   unsigned i = 0;
474   MachineInstr &MI = *II;
475   MachineFunction &MF = *MI.getParent()->getParent();
476   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
477 
478   while (!MI.getOperand(i).isFI()) {
479     ++i;
480     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
481   }
482 
483   int FrameIndex = MI.getOperand(i).getIndex();
484   unsigned BasePtr;
485 
486   unsigned Opc = MI.getOpcode();
487   bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
488   if (needsStackRealignment(MF))
489     BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
490   else if (AfterFPPop)
491     BasePtr = StackPtr;
492   else
493     BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
494 
495   // This must be part of a four operand memory reference.  Replace the
496   // FrameIndex with base register with EBP.  Add an offset to the offset.
497   MI.getOperand(i).ChangeToRegister(BasePtr, false);
498 
499   // Now add the frame object offset to the offset from EBP.
500   int FIOffset;
501   if (AfterFPPop) {
502     // Tail call jmp happens after FP is popped.
503     const MachineFrameInfo *MFI = MF.getFrameInfo();
504     FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
505   } else
506     FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
507 
508   if (MI.getOperand(i+3).isImm()) {
509     // Offset is a 32-bit integer.
510     int Imm = (int)(MI.getOperand(i + 3).getImm());
511     int Offset = FIOffset + Imm;
512     assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
513            "Requesting 64-bit offset in 32-bit immediate!");
514     MI.getOperand(i + 3).ChangeToImmediate(Offset);
515   } else {
516     // Offset is symbolic. This is extremely rare.
517     uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
518     MI.getOperand(i+3).setOffset(Offset);
519   }
520 }
521 
getFrameRegister(const MachineFunction & MF) const522 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
523   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
524   return TFI->hasFP(MF) ? FramePtr : StackPtr;
525 }
526 
getEHExceptionRegister() const527 unsigned X86RegisterInfo::getEHExceptionRegister() const {
528   llvm_unreachable("What is the exception register");
529 }
530 
getEHHandlerRegister() const531 unsigned X86RegisterInfo::getEHHandlerRegister() const {
532   llvm_unreachable("What is the exception handler register");
533 }
534 
535 namespace llvm {
getX86SubSuperRegister(unsigned Reg,EVT VT,bool High)536 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
537   switch (VT.getSimpleVT().SimpleTy) {
538   default: return Reg;
539   case MVT::i8:
540     if (High) {
541       switch (Reg) {
542       default: return getX86SubSuperRegister(Reg, MVT::i64, High);
543       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
544         return X86::AH;
545       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
546         return X86::DH;
547       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
548         return X86::CH;
549       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
550         return X86::BH;
551       }
552     } else {
553       switch (Reg) {
554       default: return 0;
555       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
556         return X86::AL;
557       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
558         return X86::DL;
559       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
560         return X86::CL;
561       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
562         return X86::BL;
563       case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
564         return X86::SIL;
565       case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
566         return X86::DIL;
567       case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
568         return X86::BPL;
569       case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
570         return X86::SPL;
571       case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
572         return X86::R8B;
573       case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
574         return X86::R9B;
575       case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
576         return X86::R10B;
577       case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
578         return X86::R11B;
579       case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
580         return X86::R12B;
581       case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
582         return X86::R13B;
583       case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
584         return X86::R14B;
585       case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
586         return X86::R15B;
587       }
588     }
589   case MVT::i16:
590     switch (Reg) {
591     default: return Reg;
592     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
593       return X86::AX;
594     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
595       return X86::DX;
596     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
597       return X86::CX;
598     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
599       return X86::BX;
600     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
601       return X86::SI;
602     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
603       return X86::DI;
604     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
605       return X86::BP;
606     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
607       return X86::SP;
608     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
609       return X86::R8W;
610     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
611       return X86::R9W;
612     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
613       return X86::R10W;
614     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
615       return X86::R11W;
616     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
617       return X86::R12W;
618     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
619       return X86::R13W;
620     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
621       return X86::R14W;
622     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
623       return X86::R15W;
624     }
625   case MVT::i32:
626     switch (Reg) {
627     default: return Reg;
628     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
629       return X86::EAX;
630     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
631       return X86::EDX;
632     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
633       return X86::ECX;
634     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
635       return X86::EBX;
636     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
637       return X86::ESI;
638     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
639       return X86::EDI;
640     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
641       return X86::EBP;
642     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
643       return X86::ESP;
644     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
645       return X86::R8D;
646     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
647       return X86::R9D;
648     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
649       return X86::R10D;
650     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
651       return X86::R11D;
652     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
653       return X86::R12D;
654     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
655       return X86::R13D;
656     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
657       return X86::R14D;
658     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
659       return X86::R15D;
660     }
661   case MVT::i64:
662     // For 64-bit mode if we've requested a "high" register and the
663     // Q or r constraints we want one of these high registers or
664     // just the register name otherwise.
665     if (High) {
666       switch (Reg) {
667       case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
668         return X86::SI;
669       case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
670         return X86::DI;
671       case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
672         return X86::BP;
673       case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
674         return X86::SP;
675       // Fallthrough.
676       }
677     }
678     switch (Reg) {
679     default: return Reg;
680     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
681       return X86::RAX;
682     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
683       return X86::RDX;
684     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
685       return X86::RCX;
686     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
687       return X86::RBX;
688     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
689       return X86::RSI;
690     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
691       return X86::RDI;
692     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
693       return X86::RBP;
694     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
695       return X86::RSP;
696     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
697       return X86::R8;
698     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
699       return X86::R9;
700     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
701       return X86::R10;
702     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
703       return X86::R11;
704     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
705       return X86::R12;
706     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
707       return X86::R13;
708     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
709       return X86::R14;
710     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
711       return X86::R15;
712     }
713   }
714 }
715 }
716 
717 namespace {
718   struct MSAH : public MachineFunctionPass {
719     static char ID;
MSAH__anone54d7f580111::MSAH720     MSAH() : MachineFunctionPass(ID) {}
721 
runOnMachineFunction__anone54d7f580111::MSAH722     virtual bool runOnMachineFunction(MachineFunction &MF) {
723       const X86TargetMachine *TM =
724         static_cast<const X86TargetMachine *>(&MF.getTarget());
725       const TargetFrameLowering *TFI = TM->getFrameLowering();
726       MachineRegisterInfo &RI = MF.getRegInfo();
727       X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
728       unsigned StackAlignment = TFI->getStackAlignment();
729 
730       // Be over-conservative: scan over all vreg defs and find whether vector
731       // registers are used. If yes, there is a possibility that vector register
732       // will be spilled and thus require dynamic stack realignment.
733       for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
734         unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
735         if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
736           FuncInfo->setForceFramePointer(true);
737           return true;
738         }
739       }
740       // Nothing to do
741       return false;
742     }
743 
getPassName__anone54d7f580111::MSAH744     virtual const char *getPassName() const {
745       return "X86 Maximal Stack Alignment Check";
746     }
747 
getAnalysisUsage__anone54d7f580111::MSAH748     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
749       AU.setPreservesCFG();
750       MachineFunctionPass::getAnalysisUsage(AU);
751     }
752   };
753 
754   char MSAH::ID = 0;
755 }
756 
757 FunctionPass*
createX86MaxStackAlignmentHeuristicPass()758 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }
759