Home
last modified time | relevance | path

Searched refs:R8 (Results 1 – 25 of 61) sorted by relevance

123

/external/llvm/test/TableGen/
DTargetInstrInfo.td35 def R8 : RegisterClass;
87 def MOV8rr : Inst<(ops R8:$dst, R8:$src),
89 [(set R8:$dst, R8:$src)]>;
92 def MOV8ri : Inst<(ops R8:$dst, imm8:$src),
94 [(set R8:$dst, imm8:$src)]>;
101 def AND8rr : Inst<(ops R8:$dst, R8:$src1, R8:$src2),
103 [(set R8:$dst, (and R8:$src1, R8:$src2))]>;
/external/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.cpp303 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, in getRawAllocationOrder()
310 ARM::R8, ARM::R10 in getRawAllocationOrder()
315 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, in getRawAllocationOrder()
322 ARM::R8, ARM::R10 in getRawAllocationOrder()
327 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, in getRawAllocationOrder()
334 ARM::R8 in getRawAllocationOrder()
340 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, in getRawAllocationOrder()
345 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, in getRawAllocationOrder()
352 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, in getRawAllocationOrder()
357 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, in getRawAllocationOrder()
[all …]
DThumb1InstrInfo.cpp31 NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); in getNoopForMachoTarget()
32 NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); in getNoopForMachoTarget()
DARMBaseRegisterInfo.h45 case R8: case R9: case R10: case R11: in isARMArea1Register()
56 case R8: case R9: case R10: case R11: in isARMArea2Register()
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td34 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
51 R4, R5, R6, R7, R8, R9, R10)>;
/external/llvm/lib/Target/MBlaze/MCTargetDesc/
DMBlazeBaseInfo.h113 case MBlaze::R8 : return 8; in getMBlazeRegisterNumbering()
177 case 8 : return MBlaze::R8; in getMBlazeRegisterFromNumbering()
/external/llvm/lib/Target/CellSPU/
DSPUCallingConv.td21 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
38 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
/external/valgrind/main/VEX/orig_ppc32/
Dreturn0.orig254 9: PUTL t8, R8
271 20: GETL R8, t14
280 27: PUTL t18, R8
434 1: GETL R8, t2
523 10: GETL R8, t8
660 0: GETL R8, t0
703 15: GETL R8, t12
746 15: GETL R8, t12
789 15: GETL R8, t12
832 15: GETL R8, t12
[all …]
Ddate.orig254 9: PUTL t8, R8
271 20: GETL R8, t14
280 27: PUTL t18, R8
434 1: GETL R8, t2
523 10: GETL R8, t8
660 0: GETL R8, t0
703 15: GETL R8, t12
746 15: GETL R8, t12
789 15: GETL R8, t12
832 15: GETL R8, t12
[all …]
/external/kernel-headers/original/asm-x86/
Dptrace-abi.h38 #define R8 72 macro
/external/llvm/lib/Target/X86/
DX86RegisterInfo.cpp97 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: in getSEHRegNum()
308 X86::R8, X86::R9, X86::R10, X86::R11, in getReservedRegs()
571 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: in getX86SubSuperRegister()
608 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: in getX86SubSuperRegister()
644 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: in getX86SubSuperRegister()
696 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: in getX86SubSuperRegister()
697 return X86::R8; in getX86SubSuperRegister()
DX86CallingConv.td148 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
215 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
218 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
224 [RCX , RDX , R8 , R9 ]>>,
241 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
DX86RegisterInfo.td135 def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
313 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
357 R8, R9, R11, RIP)> {
364 R8, R9, R11)>;
/external/llvm/lib/Target/PowerPC/
DPPCCallingConv.td21 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
38 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
71 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCBaseInfo.h39 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; in getPPCRegisterNumbering()
/external/valgrind/main/coregrind/m_sigframe/
Dsigframe-arm-linux.c146 SC2(r8,R8); in synth_ucontext()
320 REST(r8,R8); in VG_()
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td72 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
107 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
/external/llvm/test/MC/Disassembler/X86/
Dintel-syntax.txt30 # CHECK: xchg RAX, R8
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h168 ENTRY(R8) \
186 ENTRY(R8) \
/external/llvm/test/CodeGen/Mips/
Datomic.ll209 ; CHECK: andi $[[R8:[0-9]+]], $4, 255
210 ; CHECK: sllv $[[R9:[0-9]+]], $[[R8]], $[[R4]]
/external/valgrind/main/VEX/auxprogs/
Dgenoffsets.c108 GENOFFSET(AMD64,amd64,R8); in foo()
/external/llvm/test/CodeGen/X86/
Dghc-cc64.ll12 @r5 = external global i64 ; assigned to register: R8
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp229 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: in getX86RegNum()
308 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: in InitLLVM2SEHRegisterMapping()
/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/en-US/
Den-US_lh0_kdt_lfz3.pkb65 �%���n��)0�N�@���8��|7��$��aXP�8�����@:�VT2n���6� E���R8P����$��(@T�6…
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMBaseInfo.h163 case R8: case S8: case D8: case Q8: return 8; in getARMRegisterNumbering()

123