| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfoImpl.cpp | 79 unsigned Reg1 = MI->getOperand(Idx1).getReg(); in commuteInstruction() local
88 if (HasDef && Reg0 == Reg1 && in commuteInstruction()
96 Reg0 = Reg1; in commuteInstruction()
108 .addReg(Reg1, getKillRegState(Reg1IsKill), SubReg1); in commuteInstruction()
112 .addReg(Reg1, getKillRegState(Reg1IsKill), SubReg1); in commuteInstruction()
119 MI->getOperand(Idx2).setReg(Reg1); in commuteInstruction()
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| D | AggressiveAntiDepBreaker.h | 104 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
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| D | StrongPHIElimination.cpp | 438 void StrongPHIElimination::unionRegs(unsigned Reg1, unsigned Reg2) { in unionRegs() argument
439 Node *Node1 = RegNodeMap[Reg1]->getLeader(); in unionRegs()
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| D | AggressiveAntiDepBreaker.cpp | 80 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) in UnionGroups() argument
86 unsigned Group1 = GetGroup(Reg1); in UnionGroups()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 115 unsigned Reg1, bool isKill1, in addRegReg() argument
117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
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| D | X86FastISel.cpp | 1471 unsigned Reg1 = getRegForValue(Op1); in X86VisitIntrinsicCall() local
1474 if (Reg1 == 0 || Reg2 == 0) in X86VisitIntrinsicCall()
1490 .addReg(Reg1).addReg(Reg2); in X86VisitIntrinsicCall()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 76 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
77 return contains(Reg1) && contains(Reg2); in contains()
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 1029 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwo() local
1030 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}"; in printVectorListTwo()
1038 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpaced() local
1039 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}"; in printVectorListTwoSpaced()
1074 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwoAllLanes() local
1075 O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}"; in printVectorListTwoAllLanes()
1106 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpacedAllLanes() local
1107 O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}"; in printVectorListTwoSpacedAllLanes()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 80 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
81 return MC->contains(Reg1, Reg2); in contains()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 137 unsigned Reg1 = MI->getOperand(1).getReg(); in commuteInstruction() local
144 if (Reg0 == Reg1) { in commuteInstruction()
163 .addReg(Reg1, getKillRegState(Reg1IsKill)) in commuteInstruction()
170 MI->getOperand(2).setReg(Reg1); in commuteInstruction()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 599 unsigned Reg1 = MI->getOperand(1).getReg(); in ReduceTo2Addr() local
604 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
610 if (Reg1 != Reg0) in ReduceTo2Addr()
617 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
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| D | ARMBaseInstrInfo.cpp | 2050 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); in FoldImmediate() local
2056 .addReg(Reg1, getKillRegState(isKill)) in FoldImmediate()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 876 CodeGenRegister *Reg1 = Registers[i]; in computeComposites() local
877 const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs(); in computeComposites()
883 if (Reg1 == Reg2) in computeComposites()
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