| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfoImpl.cpp | 80 unsigned Reg2 = MI->getOperand(Idx2).getReg(); in commuteInstruction() local
91 Reg0 = Reg2; in commuteInstruction()
93 } else if (HasDef && Reg0 == Reg2 && in commuteInstruction()
107 .addReg(Reg2, getKillRegState(Reg2IsKill), SubReg2) in commuteInstruction()
111 .addReg(Reg2, getKillRegState(Reg2IsKill), SubReg2) in commuteInstruction()
120 MI->getOperand(Idx1).setReg(Reg2); in commuteInstruction()
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| D | AggressiveAntiDepBreaker.h | 104 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
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| D | StrongPHIElimination.cpp | 438 void StrongPHIElimination::unionRegs(unsigned Reg1, unsigned Reg2) { in unionRegs() argument
440 Node *Node2 = RegNodeMap[Reg2]->getLeader(); in unionRegs()
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| D | AggressiveAntiDepBreaker.cpp | 80 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) in UnionGroups() argument
87 unsigned Group2 = GetGroup(Reg2); in UnionGroups()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 116 unsigned Reg2, bool isKill2) { in addRegReg() argument
118 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
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| D | X86FastISel.cpp | 1472 unsigned Reg2 = getRegForValue(Op2); in X86VisitIntrinsicCall() local
1474 if (Reg1 == 0 || Reg2 == 0) in X86VisitIntrinsicCall()
1490 .addReg(Reg1).addReg(Reg2); in X86VisitIntrinsicCall()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 76 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
77 return contains(Reg1) && contains(Reg2); in contains()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 138 unsigned Reg2 = MI->getOperand(2).getReg(); in commuteInstruction() local
158 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); in commuteInstruction()
162 .addReg(Reg2, getKillRegState(Reg2IsKill)) in commuteInstruction()
169 MI->getOperand(0).setReg(Reg2); in commuteInstruction()
171 MI->getOperand(1).setReg(Reg2); in commuteInstruction()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 80 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
81 return MC->contains(Reg1, Reg2); in contains()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 602 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
605 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()
607 if (Reg0 != Reg2) { in ReduceTo2Addr()
635 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
636 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 881 CodeGenRegister *Reg2 = i1->second; in computeComposites() local
883 if (Reg1 == Reg2) in computeComposites()
885 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); in computeComposites()
892 if (Reg2 == Reg3) in computeComposites()
1347 CodeGenRegister *Reg2 = getReg(RegList[i2]); in computeOverlaps() local
1348 CodeGenRegister::Set &Overlaps2 = Map[Reg2]; in computeOverlaps()
1349 const CodeGenRegister::SuperRegList &Supers2 = Reg2->getSuperRegs(); in computeOverlaps()
1351 Overlaps.insert(Reg2); in computeOverlaps()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2053 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32() local
2054 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) in CC_MipsO32()
2817 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), in LowerFormalArguments() local
2819 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); in LowerFormalArguments()
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