| /external/llvm/test/CodeGen/ARM/ |
| D | 2010-04-09-NeonSelect.ll | 2 ; Radar 7770501: Don't crash on SELECT and SELECT_CC with NEON vector values.
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.td | 379 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
382 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
384 "${:comment} SELECT_CC PSEUDO!",
1144 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1147 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1150 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1152 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1154 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1156 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1158 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
[all …]
|
| D | XCoreISelLowering.cpp | 87 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in XCoreTargetLowering()
94 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in XCoreTargetLowering()
177 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
1271 assert((MI->getOpcode() == XCore::SELECT_CC) && in EmitInstrWithCustomInserter()
|
| /external/llvm/lib/Target/PTX/ |
| D | PTXISelLowering.cpp | 83 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in PTXTargetLowering()
84 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in PTXTargetLowering()
85 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in PTXTargetLowering()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 116 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); in MSP430TargetLowering()
117 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); in MSP430TargetLowering()
191 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
833 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size()); in LowerSETCC()
856 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size()); in LowerSELECT_CC()
978 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC"; in getTargetNodeName()
|
| D | MSP430ISelLowering.h | 62 SELECT_CC, enumerator
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 335 SELECT_CC, enumerator
|
| D | SelectionDAG.h | 582 return getNode(ISD::SELECT_CC, DL, True.getValueType(),
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeFloatTypes.cpp | 95 case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N); break; in SoftenFloatResult()
512 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), in SoftenFloatRes_SELECT_CC()
590 case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break; in SoftenFloatOperand()
839 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in ExpandFloatResult()
904 Lo = DAG.getNode(ISD::SELECT_CC, dl, Lo.getValueType(), Tmp, Hi, Lo, in ExpandFloatRes_FABS()
1230 Lo = DAG.getNode(ISD::SELECT_CC, dl, VT, Src, DAG.getConstant(0, SrcVT), in ExpandFloatRes_XINT_TO_FP()
1269 case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break; in ExpandFloatOperand()
1386 return DAG.getNode(ISD::SELECT_CC, dl, MVT::i32, N->getOperand(0), Tmp, in ExpandFloatOp_FP_TO_UINT()
|
| D | LegalizeTypesGeneric.cpp | 470 Lo = DAG.getNode(ISD::SELECT_CC, dl, LL.getValueType(), N->getOperand(0), in SplitRes_SELECT_CC()
472 Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0), in SplitRes_SELECT_CC()
|
| D | LegalizeVectorTypes.cpp | 63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; in ScalarizeVectorResult()
270 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(), in ScalarizeVecRes_SELECT_CC()
456 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in SplitVectorResult()
1254 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; in WidenVectorResult()
1952 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), in WidenVecRes_SELECT_CC()
|
| D | SelectionDAGDumper.cpp | 189 case ISD::SELECT_CC: return "select_cc"; in getOperationName()
|
| D | LegalizeVectorOps.cpp | 195 case ISD::SELECT_CC: in LegalizeOp()
|
| D | LegalizeIntegerTypes.cpp | 69 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; in PromoteIntegerResult()
505 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), in PromoteIntRes_SELECT_CC()
779 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; in PromoteIntegerOperand()
1093 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in ExpandIntegerResult()
2451 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; in ExpandIntegerOperand()
|
| D | LegalizeDAG.cpp | 747 case ISD::SELECT_CC: in LegalizeOp()
750 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : in LegalizeOp()
758 if (Node->getOpcode() == ISD::SELECT_CC) in LegalizeOp()
3395 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, in ExpandNode()
3400 case ISD::SELECT_CC: { in ExpandNode()
3413 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, in ExpandNode()
|
| D | DAGCombiner.cpp | 543 if (N.getOpcode() == ISD::SELECT_CC && in isSetCCEquivalent()
1122 case ISD::SELECT_CC: return visitSELECT_CC(N); in visit()
3322 case ISD::SELECT_CC: in visitXOR()
4056 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && in visitSELECT()
4057 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) in visitSELECT()
4058 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, in visitSELECT()
4093 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), in visitSELECT_CC()
8072 if (SCC.getOpcode() == ISD::SELECT_CC) { in SimplifySelect()
8156 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), in SimplifySelectOps()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1218 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in HexagonTargetLowering()
1219 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in HexagonTargetLowering()
1222 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in HexagonTargetLowering()
1360 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
|
| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 130 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in MBlazeTargetLowering()
144 AddPromotedToType(ISD::SELECT_CC, MVT::i1, MVT::i32); in MBlazeTargetLowering()
205 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
|
| D | MBlazeInstrInfo.td | 612 "; SELECT_CC PSEUDO!",
848 // SELECT_CC
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 746 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SparcTargetLowering()
747 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SparcTargetLowering()
748 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in SparcTargetLowering()
1155 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
|
| D | SparcInstrInfo.td | 252 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
|
| /external/llvm/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 165 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in SPUTargetLowering()
166 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); in SPUTargetLowering()
167 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); in SPUTargetLowering()
168 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SPUTargetLowering()
169 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in SPUTargetLowering()
2850 case ISD::SELECT_CC: in LowerOperation()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 1001 case ISD::SELECT_CC: { in Select()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 125 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand); in addTypeForNEON()
553 setTargetDAGCombine(ISD::SELECT_CC); in ARMTargetLowering()
747 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in ARMTargetLowering()
748 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in ARMTargetLowering()
749 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in ARMTargetLowering()
5146 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
6656 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; in combineSelectAndUse()
8433 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
|
| /external/llvm/lib/Target/X86/ |
| D | README-SSE.txt | 546 just be a matter of having scalar sse map to SELECT_CC and custom expanding
|