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Searched refs:SETLT (Results 1 – 24 of 24) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h734 SETLT, // 1 X 1 0 0 True if less than enumerator
745 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td43 IntRegs:$fval, SETLT)),
113 DoubleRegs:$fval, SETLT)),
DHexagonISelDAGToDAG.cpp831 if (cast<CondCodeSDNode>(N02)->get() == ISD::SETLT) { in SelectSelect()
/external/llvm/lib/CodeGen/
DAnalysis.cpp178 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
197 case ICmpInst::ICMP_SLT: return ISD::SETLT; in getICmpCondCode()
/external/llvm/lib/Target/MBlaze/
DMBlazeInstrInfo.td769 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETLT),
794 def : Pat<(setcc (i32 0), (i32 GPR:$R), SETLT),
822 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLT),
859 (i32 GPR:$T), (i32 GPR:$F), SETLT),
890 (i32 GPR:$T), (i32 GPR:$F), SETLT),
921 (i32 GPR:$T), (i32 GPR:$F), SETLT),
957 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETLT), bb:$T),
978 def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETLT), bb:$T),
999 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETLT), bb:$T),
DMBlazeInstrFPU.td160 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLT),
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp556 case ISD::SETLT: return PPC::PRED_LT; in getPredicateForSetCC()
583 case ISD::SETLT: return 0; // Bit #0 = SETOLT in getCRIdxForSetCC()
635 case ISD::SETLT: { in SelectSETCC()
668 case ISD::SETLT: { in SelectSETCC()
DPPCISelLowering.cpp1361 DAG.getConstant(8, MVT::i32), ISD::SETLT); in LowerVAARG()
3643 case ISD::SETLT: in LowerSELECT_CC()
3665 case ISD::SETLT: in LowerSELECT_CC()
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp509 CCs[RTLIB::OLT_F32] = ISD::SETLT; in InitCmpLibcallCCs()
510 CCs[RTLIB::OLT_F64] = ISD::SETLT; in InitCmpLibcallCCs()
2111 case ISD::SETLT: in SimplifySetCC()
2271 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); in SimplifySetCC()
2274 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) in SimplifySetCC()
2287 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) in SimplifySetCC()
2291 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) in SimplifySetCC()
2309 ISD::SETLT); in SimplifySetCC()
2591 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X in SimplifySetCC()
DSelectionDAGDumper.cpp303 case ISD::SETLT: return "setlt"; in getOperationName()
DLegalizeIntegerTypes.cpp835 case ISD::SETLT: in PromoteSetCCOperands()
2517 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 in IntegerExpandSetCCOperands()
2528 case ISD::SETLT: in IntegerExpandSetCCOperands()
2565 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || in IntegerExpandSetCCOperands()
2810 ISD::SETLT); in ExpandIntOp_UINT_TO_FP()
DLegalizeDAG.cpp1510 ISD::SETLT); in ExpandFCOPYSIGN()
1576 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; in LegalizeSetCCCondCode()
1582 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; in LegalizeSetCCCondCode()
2125 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT); in ExpandLegalINT_TO_FP()
2164 ISD::SETLT); in ExpandLegalINT_TO_FP()
2718 Tmp1, ISD::SETLT); in ExpandNode()
DLegalizeFloatTypes.cpp635 case ISD::SETLT: in SoftenSetCCOperands()
1231 Lo, Hi, DAG.getCondCode(ISD::SETLT)); in ExpandFloatRes_XINT_TO_FP()
DDAGCombiner.cpp3023 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { in visitOR()
8233 if ((CC == ISD::SETLT || CC == ISD::SETLE) && in SimplifySelectCC()
8294 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && in SimplifySelectCC()
8459 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || in SimplifySelectCC()
8460 (N1C->isOne() && CC == ISD::SETLT)) && in SimplifySelectCC()
DSelectionDAG.cpp256 case ISD::SETLT: in isSignedOp()
1549 case ISD::SETLT: return getConstant(C1.slt(C2), VT); in FoldSetCC()
1574 case ISD::SETLT: if (R==APFloat::cmpUnordered) in FoldSetCC()
DSelectionDAGBuilder.cpp2264 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); in handleBTSplitSwitchCase()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp649 case ISD::SETLT: return SPCC::ICC_L; in IntCondCCodeToICC()
669 case ISD::SETLT: in FPCondCCodeToFCC()
/external/llvm/lib/Target/PTX/
DPTXInstrInfo.td553 defm SETPLTs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETLT, "lt">;
566 defm SETPLTs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETLT, "lt">;
579 defm SETPLTs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETLT, "lt">;
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td500 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
851 (setcc node:$lhs, node:$rhs, SETLT)>;
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp724 case ISD::SETLT: in EmitCMP()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp1091 case ISD::SETLT: return ARMCC::LT; in IntCCToARMCC()
1120 case ISD::SETLT: in FPCCToARMCC()
2746 case ISD::SETLT: in getARMCmp()
2749 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; in getARMCmp()
2763 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; in getARMCmp()
3576 case ISD::SETLT: Swap = true; // Fallthrough in LowerVSETCC()
3612 case ISD::SETLT: Swap = true; in LowerVSETCC()
8293 case ISD::SETLT: in PerformSELECT_CCCombine()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp3055 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { in TranslateX86CC()
3058 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { in TranslateX86CC()
3070 case ISD::SETLT: return X86::COND_L; in TranslateX86CC()
3117 case ISD::SETLT: return X86::COND_B; in TranslateX86CC()
7770 ISD::SETLT); in LowerUINT_TO_FP()
8414 case ISD::SETLT: in LowerVSETCC()
8470 case ISD::SETLT: Swap = true; in LowerVSETCC()
9277 CC = ISD::SETLT; in LowerINTRINSIC_WO_CHAIN()
9307 CC = ISD::SETLT; in LowerINTRINSIC_WO_CHAIN()
13330 case ISD::SETLT: in PerformSELECTCombine()
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/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp513 case ISD::SETLT: in FPCondCCodeToFCC()
/external/llvm/lib/Target/CellSPU/
DSPUISelLowering.cpp2597 compareOp = ISD::SETLT; break; in LowerSETCC()