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Searched refs:SETNE (Results 1 – 24 of 24) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td20 IntRegs:$fval, SETNE)),
80 // and similarly for SETNE
83 IntRegs:$fval, SETNE)),
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp505 CCs[RTLIB::UNE_F32] = ISD::SETNE; in InitCmpLibcallCCs()
506 CCs[RTLIB::UNE_F64] = ISD::SETNE; in InitCmpLibcallCCs()
515 CCs[RTLIB::UO_F32] = ISD::SETNE; in InitCmpLibcallCCs()
516 CCs[RTLIB::UO_F64] = ISD::SETNE; in InitCmpLibcallCCs()
1957 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1962 Cond = ISD::SETNE; in SimplifySetCC()
1991 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
2000 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { in SimplifySetCC()
2106 case ISD::SETNE: return DAG.getConstant(1, VT); in SimplifySetCC()
2123 case ISD::SETNE: in SimplifySetCC()
[all …]
DLegalizeIntegerTypes.cpp467 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_SADDSUBO()
633 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_UADDSUBO()
670 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE); in PromoteIntRes_XMULO()
675 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE); in PromoteIntRes_XMULO()
822 case ISD::SETNE: in PromoteSetCCOperands()
1718 DAG.getConstant(0, NVT), ISD::SETNE); in ExpandIntRes_CTLZ()
1748 DAG.getConstant(0, NVT), ISD::SETNE); in ExpandIntRes_CTTZ()
2025 ISD::SETEQ : ISD::SETNE); in ExpandIntRes_SADDSUBO()
2028 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); in ExpandIntRes_SADDSUBO()
2276 RHS, DAG.getConstant(0, VT), ISD::SETNE); in ExpandIntRes_XMULO()
[all …]
DLegalizeFloatTypes.cpp627 case ISD::SETNE: in SoftenSetCCOperands()
721 CCCode = ISD::SETNE; in SoftenFloatOp_BR_CC()
763 CCCode = ISD::SETNE; in SoftenFloatOp_SELECT_CC()
1332 CCCode = ISD::SETNE; in ExpandFloatOp_BR_CC()
1413 CCCode = ISD::SETNE; in ExpandFloatOp_SELECT_CC()
DLegalizeDAG.cpp1578 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; in LegalizeSetCCCondCode()
1584 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; in LegalizeSetCCCondCode()
2138 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE); in ExpandLegalINT_TO_FP()
3198 ISD::SETEQ : ISD::SETNE); in ExpandNode()
3201 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); in ExpandNode()
3293 ISD::SETNE); in ExpandNode()
3296 DAG.getConstant(0, VT), ISD::SETNE); in ExpandNode()
3323 Tmp2, Tmp3, ISD::SETNE); in ExpandNode()
3374 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
3412 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
[all …]
DSelectionDAGDumper.cpp305 case ISD::SETNE: return "setne"; in getOperationName()
DSelectionDAG.cpp255 case ISD::SETNE: return 0; in isSignedOp()
286 Op = ISD::SETNE; in getSetCCOrOperation()
1544 case ISD::SETNE: return getConstant(C1 != C2, VT); in FoldSetCC()
1569 case ISD::SETNE: if (R==APFloat::cmpUnordered) in FoldSetCC()
DDAGCombiner.cpp3023 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { in visitOR()
3032 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { in visitOR()
4433 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE) in isTruncateOf()
6174 ISD::SETNE); in visitBRCOND()
6240 Equal ? ISD::SETEQ : ISD::SETNE); in visitBRCOND()
DSelectionDAGBuilder.cpp1463 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) in ShouldEmitAsBranches()
1785 ISD::SETNE); in visitBitTestCase()
1797 ISD::SETNE); in visitBitTestCase()
5474 ISD::SETNE); in visitMemCmpCall()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp452 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
493 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
554 case ISD::SETNE: return PPC::PRED_NE; in getPredicateForSetCC()
594 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE in getCRIdxForSetCC()
627 case ISD::SETNE: { in SelectSETCC()
660 case ISD::SETNE: { in SelectSETCC()
1012 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE && in Select()
DPPCISelLowering.cpp1292 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
1324 DAG.getConstant(0, MVT::i32), ISD::SETNE); in LowerVAARG()
3629 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op; in LowerSELECT_CC()
5447 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && in PerformDAGCombine()
/external/llvm/lib/CodeGen/
DAnalysis.cpp177 case ISD::SETONE: case ISD::SETUNE: return ISD::SETNE; in getFCmpCodeWithoutNaN()
192 case ICmpInst::ICMP_NE: return ISD::SETNE; in getICmpCondCode()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h736 SETNE, // 1 X 1 1 0 True if not equal enumerator
/external/llvm/lib/Target/MBlaze/
DMBlazeInstrInfo.td765 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETNE),
790 def : Pat<(setcc (i32 0), (i32 GPR:$R), SETNE),
816 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETNE),
853 (i32 GPR:$T), (i32 GPR:$F), SETNE),
884 (i32 GPR:$T), (i32 GPR:$F), SETNE),
915 (i32 GPR:$T), (i32 GPR:$F), SETNE),
953 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETNE), bb:$T),
974 def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETNE), bb:$T),
995 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETNE), bb:$T),
DMBlazeInstrFPU.td143 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETNE),
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp205 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); in ARMTargetLowering()
206 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); in ARMTargetLowering()
207 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); in ARMTargetLowering()
208 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); in ARMTargetLowering()
209 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); in ARMTargetLowering()
210 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); in ARMTargetLowering()
211 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); in ARMTargetLowering()
224 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); in ARMTargetLowering()
225 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); in ARMTargetLowering()
226 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); in ARMTargetLowering()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrCMovSetCC.td99 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
DX86ISelLowering.cpp3072 case ISD::SETNE: return X86::COND_NE; in TranslateX86CC()
3122 case ISD::SETNE: return X86::COND_NE; in TranslateX86CC()
8312 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
8323 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
8329 bool Invert = (CC == ISD::SETNE) ^ in LowerSETCC()
8422 case ISD::SETNE: SSECC = 4; break; in LowerVSETCC()
8468 case ISD::SETNE: Invert = true; in LowerVSETCC()
8665 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); in LowerSELECT()
8971 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); in LowerBRCOND()
9297 CC = ISD::SETNE; in LowerINTRINSIC_WO_CHAIN()
[all …]
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp648 case ISD::SETNE: return SPCC::ICC_NE; in IntCondCCodeToICC()
667 case ISD::SETNE: in FPCondCCodeToFCC()
864 CC == ISD::SETNE && in LookThroughSetCC()
/external/llvm/lib/Target/PTX/
DPTXInstrInfo.td548 defm SETPNEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETNE, "ne">;
561 defm SETPNEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETNE, "ne">;
574 defm SETPNEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETNE, "ne">;
1023 def : Pat<(i1 (setcc RegPred:$a, imm:$b, SETNE)),
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td500 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
855 (setcc node:$lhs, node:$rhs, SETNE)>;
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp676 case ISD::SETNE: in EmitCMP()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp527 case ISD::SETNE: in FPCondCCodeToFCC()
/external/llvm/lib/Target/CellSPU/
DSPUISelLowering.cpp2603 compareOp = ISD::SETNE; break; in LowerSETCC()