| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 723 SETUGT, // 1 0 1 0 True if unordered or greater than enumerator
751 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
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| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 164 case FCmpInst::FCMP_UGT: return ISD::SETUGT; in getFCmpCondCode()
180 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
200 case ICmpInst::ICMP_UGT: return ISD::SETUGT; in getICmpCondCode()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.td | 775 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETUGT),
800 def : Pat<(setcc (i32 0), (i32 GPR:$R), SETUGT),
831 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT),
868 (i32 GPR:$T), (i32 GPR:$F), SETUGT),
899 (i32 GPR:$T), (i32 GPR:$F), SETUGT),
930 (i32 GPR:$T), (i32 GPR:$F), SETUGT),
963 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETUGT), bb:$T),
984 def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETUGT), bb:$T),
1005 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT), bb:$T),
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| D | MBlazeInstrFPU.td | 188 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGT),
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| /external/llvm/lib/Target/CellSPU/ |
| D | README.txt | 76 SETUGT unimplemented
|
| D | SPUISelLowering.cpp | 2590 case ISD::SETUGT: in LowerSETCC()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 1987 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
2101 case ISD::SETUGT: in SimplifySetCC()
2124 case ISD::SETUGT: in SimplifySetCC()
2263 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); in SimplifySetCC()
2278 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) in SimplifySetCC()
2284 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) in SimplifySetCC()
2296 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) in SimplifySetCC()
2305 if (Cond == ISD::SETUGT && in SimplifySetCC()
2390 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) in SimplifySetCC()
2391 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); in SimplifySetCC()
[all …]
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| D | SelectionDAGDumper.cpp | 294 case ISD::SETUGT: return "setugt"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 824 case ISD::SETUGT: in PromoteSetCCOperands()
2251 ISD::SETULT : ISD::SETUGT); in ExpandIntRes_UADDSUBO()
2531 case ISD::SETUGT: LowCC = ISD::SETUGT; break; in IntegerExpandSetCCOperands()
2566 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { in IntegerExpandSetCCOperands()
|
| D | SelectionDAG.cpp | 262 case ISD::SETUGT: in isSignedOp()
312 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE in getSetCCAndOperation()
1546 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); in FoldSetCC()
1599 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || in FoldSetCC()
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| D | LegalizeDAG.cpp | 1580 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; in LegalizeSetCCCondCode()
2935 Tmp1, Tmp2, ISD::SETUGT); in ExpandNode()
3217 ISD::SETULT : ISD::SETUGT)); in ExpandNode()
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| D | LegalizeFloatTypes.cpp | 660 case ISD::SETUGT: in SoftenSetCCOperands()
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| D | SelectionDAGBuilder.cpp | 1677 ISD::SETUGT); in visitJumpTableHeader()
1712 ISD::SETUGT); in visitBitTestHeader()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSelectCCInfo.td | 30 IntRegs:$fval, SETUGT)),
|
| /external/llvm/lib/Target/PTX/ |
| D | PTXInstrInfo.td | 551 defm SETPGTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGT, "gt">;
564 defm SETPGTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGT, "gt">;
577 defm SETPGTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGT, "gt">;
590 defm SETPGTf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUGT, SETOGT, "gt">;
599 defm SETPGTf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUGT, SETOGT, "gt">;
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 567 case ISD::SETUGT: return PPC::PRED_GT; in getPredicateForSetCC()
603 case ISD::SETUGT: return 1; in getCRIdxForSetCC()
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| D | PPCISelLowering.cpp | 263 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in PPCTargetLowering()
264 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); in PPCTargetLowering()
3650 case ISD::SETUGT: in LowerSELECT_CC()
3676 case ISD::SETUGT: in LowerSELECT_CC()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 655 case ISD::SETUGT: return SPCC::ICC_GU; in IntCondCCodeToICC()
679 case ISD::SETUGT: return SPCC::FCC_UG; in FPCondCCodeToFCC()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 496 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
835 (setcc node:$lhs, node:$rhs, SETUGT)>;
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 696 case ISD::SETUGT: in EmitCMP()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1093 case ISD::SETUGT: return ARMCC::HI; in IntCCToARMCC()
1118 case ISD::SETUGT: CondCode = ARMCC::HI; break; in FPCCToARMCC()
2756 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; in getARMCmp()
2768 case ISD::SETUGT: in getARMCmp()
3585 case ISD::SETUGT: Swap = true; // Fallthrough in LowerVSETCC()
3617 case ISD::SETUGT: Opc = ARMISD::VCGTU; break; in LowerVSETCC()
8317 case ISD::SETUGT: in PerformSELECT_CCCombine()
8322 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE); in PerformSELECT_CCCombine()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 3074 case ISD::SETUGT: return X86::COND_A; in TranslateX86CC()
3093 case ISD::SETUGT: in TranslateX86CC()
3115 case ISD::SETUGT: // flipped in TranslateX86CC()
8426 case ISD::SETUGT: SSECC = 6; break; in LowerVSETCC()
8475 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break; in LowerVSETCC()
13343 case ISD::SETUGT: in PerformSELECTCombine()
13382 case ISD::SETUGT: in PerformSELECTCombine()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 523 case ISD::SETUGT: return Mips::FCOND_UGT; in FPCondCCodeToFCC()
|