| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 226 case ISD::SINT_TO_FP: in LegalizeOp()
429 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand || in ExpandUINT_TO_FLOAT()
455 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI); in ExpandUINT_TO_FLOAT()
457 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO); in ExpandUINT_TO_FLOAT()
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| D | LegalizeFloatTypes.cpp | 96 case ISD::SINT_TO_FP: in SoftenFloatResult()
540 bool Signed = N->getOpcode() == ISD::SINT_TO_FP; in SoftenFloatRes_XINT_TO_FP()
874 case ISD::SINT_TO_FP: in ExpandFloatResult()
1172 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP; in ExpandFloatRes_XINT_TO_FP()
1183 Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src); in ExpandFloatRes_XINT_TO_FP()
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| D | LegalizeDAG.cpp | 730 case ISD::SINT_TO_FP: in LegalizeOp()
2108 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0); in ExpandLegalINT_TO_FP()
2117 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or); in ExpandLegalINT_TO_FP()
2160 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2226 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { in PromoteLegalINT_TO_FP()
2227 OpToUse = ISD::SINT_TO_FP; in PromoteLegalINT_TO_FP()
2702 case ISD::SINT_TO_FP: in ExpandNode()
2704 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, in ExpandNode()
3486 Node->getOpcode() == ISD::SINT_TO_FP || in PromoteNode()
3536 case ISD::SINT_TO_FP: in PromoteNode()
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| D | LegalizeVectorTypes.cpp | 90 case ISD::SINT_TO_FP: in ScalarizeVectorResult()
504 case ISD::SINT_TO_FP: in SplitVectorResult()
997 case ISD::SINT_TO_FP: in SplitVectorOperand()
1299 case ISD::SINT_TO_FP: in WidenVectorResult()
2054 case ISD::SINT_TO_FP: in WidenVectorOperand()
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| D | SelectionDAGDumper.cpp | 223 case ISD::SINT_TO_FP: return "sint_to_fp"; in getOperationName()
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| D | FastISel.cpp | 202 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeRegForValue()
1012 return SelectCast(I, ISD::SINT_TO_FP); in SelectOperator()
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| D | LegalizeIntegerTypes.cpp | 782 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; in PromoteIntegerOperand()
2453 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; in ExpandIntegerOperand()
2781 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ in ExpandIntOp_UINT_TO_FP()
2783 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); in ExpandIntOp_UINT_TO_FP()
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| D | SelectionDAGBuilder.cpp | 2754 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); in visitSIToFP()
3623 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); in GetExponent()
3653 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); in visitExp()
4093 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); in visitExp2()
4226 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); in visitPow()
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| D | DAGCombiner.cpp | 1137 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); in visit()
5885 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); in visitSINT_TO_FP()
5889 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && in visitSINT_TO_FP()
5915 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { in visitUINT_TO_FP()
5918 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); in visitUINT_TO_FP()
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| D | SelectionDAG.cpp | 2392 case ISD::SINT_TO_FP: { in getNode()
2397 Opcode==ISD::SINT_TO_FP, in getNode()
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| /external/llvm/lib/Target/X86/ |
| D | README-FPStack.txt | 49 Add a target specific hook to DAG combiner to handle SINT_TO_FP and
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| D | X86ISelLowering.cpp | 263 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); in X86TargetLowering()
264 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); in X86TargetLowering()
269 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); in X86TargetLowering()
271 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); in X86TargetLowering()
273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); in X86TargetLowering()
274 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); in X86TargetLowering()
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); in X86TargetLowering()
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); in X86TargetLowering()
284 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); in X86TargetLowering()
761 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); in X86TargetLowering()
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 371 SINT_TO_FP, enumerator
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 348 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SPUTargetLowering()
349 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); in SPUTargetLowering()
350 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); in SPUTargetLowering()
354 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SPUTargetLowering()
390 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SPUTargetLowering()
2493 (Op.getOpcode() == ISD::SINT_TO_FP) in LowerINT_TO_FP()
2820 case ISD::SINT_TO_FP: in LowerOperation()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 110 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Custom); in addTypeForNEON()
115 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand); in addTypeForNEON()
539 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); in ARMTargetLowering()
781 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in ARMTargetLowering()
3173 case ISD::SINT_TO_FP: in LowerVectorINT_TO_FP()
3175 Opc = ISD::SINT_TO_FP; in LowerVectorINT_TO_FP()
3197 case ISD::SINT_TO_FP: in LowerINT_TO_FP()
4903 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
4904 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); in LowerSDIV_v4i8()
4933 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1087 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in HexagonTargetLowering()
1108 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 721 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1153 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); in LowerOperation()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 189 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
278 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
412 setTargetDAGCombine(ISD::SINT_TO_FP); in PPCTargetLowering()
4581 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); in LowerOperation()
5275 case ISD::SINT_TO_FP: in PerformDAGCombine()
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| D | README.txt | 546 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 390 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
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