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Searched refs:SUBE (Results 1 – 12 of 12) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h210 ADDE, SUBE, enumerator
/external/llvm/lib/Target/Mips/
DMipsISelDAGToDAG.cpp386 case ISD::SUBE: in Select()
391 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in Select()
DMipsISelLowering.cpp263 setTargetDAGCombine(ISD::SUBE); in MipsTargetLowering()
715 case ISD::SUBE: in PerformDAGCombine()
/external/llvm/lib/Target/ARM/
DARMISelLowering.h82 SUBE, // Sub using carry enumerator
DARMISelLowering.cpp618 setOperationAction(ISD::SUBE, MVT::i32, Custom); in ARMTargetLowering()
919 case ARMISD::SUBE: return "ARMISD::SUBE"; in getTargetNodeName()
5082 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
5187 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
DARMInstrInfo.td137 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp207 case ISD::SUBE: return "sube"; in getOperationName()
DLegalizeIntegerTypes.cpp1154 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; in ExpandIntegerResult()
1546 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); in ExpandIntRes_ADDSUB()
1595 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); in ExpandIntRes_ADDSUBC()
DDAGCombiner.cpp1096 case ISD::SUBE: return visitSUBE(N); in visit()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp91 setOperationAction(ISD::SUBE, MVT::i32, Expand); in XCoreTargetLowering()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td347 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp362 setOperationAction(ISD::SUBE, VT, Custom); in X86TargetLowering()
10810 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
10890 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
10953 case ISD::SUBE: in ReplaceNodeResults()