| /external/openssl/crypto/bn/asm/ |
| D | ppc.pl | 116 $UDIV= "divwu"; # unsigned divide
140 $UDIV= "divdu"; # unsigned divide
1670 $UDIV r8,r3,r9 #q = h/dh
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 182 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 148 case ISD::UDIV: { in Select()
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| D | SparcInstrInfo.td | 495 defm UDIV : F3_12np<"udiv", 0b001110>;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.h | 489 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); } in visitUDiv()
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| D | SelectionDAGDumper.cpp | 160 case ISD::UDIV: return "udiv"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 172 case ISD::UDIV: in LegalizeOp()
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| D | FastISel.cpp | 945 return SelectBinaryOp(I, ISD::UDIV); in SelectOperator()
1114 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) { in FastEmit_ri_()
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| D | LegalizeVectorTypes.cpp | 110 case ISD::UDIV: in ScalarizeVectorResult()
518 case ISD::UDIV: in SplitVectorResult()
1276 case ISD::UDIV: in WidenVectorResult()
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| D | SelectionDAG.cpp | 1715 case ISD::UDIV: { in ComputeMaskedBits()
2637 case ISD::UDIV: in FoldConstantArithmetic()
2711 case ISD::UDIV: in getNode()
3022 case ISD::UDIV: in getNode()
3050 case ISD::UDIV: in getNode()
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| D | LegalizeIntegerTypes.cpp | 112 case ISD::UDIV: in PromoteIntegerResult()
1121 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; in ExpandIntegerResult()
2279 SDValue DIV = DAG.getNode(ISD::UDIV, DL, LHS.getValueType(), MUL, NotZero); in ExpandIntRes_XMULO()
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| D | DAGCombiner.cpp | 1099 case ISD::UDIV: return visitUDIV(N); in visit()
1855 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), in visitSDIV()
1927 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); in visitUDIV()
2037 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); in visitUREM()
2277 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); in visitUDIVREM()
8018 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || in SimplifyVBinOp()
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| D | LegalizeDAG.cpp | 1929 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV; in UseDivRem()
3071 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; in ExpandNode()
3097 case ISD::UDIV: in ExpandNode()
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| D | TargetLowering.cpp | 645 case ISD::UDIV: in canOpTrap()
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 179 setOperationAction(ISD::UDIV, MVT::i8, Expand); in SPUTargetLowering()
185 setOperationAction(ISD::UDIV, MVT::i16, Expand); in SPUTargetLowering()
191 setOperationAction(ISD::UDIV, MVT::i32, Expand); in SPUTargetLowering()
197 setOperationAction(ISD::UDIV, MVT::i64, Expand); in SPUTargetLowering()
203 setOperationAction(ISD::UDIV, MVT::i128, Expand); in SPUTargetLowering()
430 setOperationAction(ISD::UDIV, VT, Expand); in SPUTargetLowering()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 154 setOperationAction(ISD::UDIV, MVT::i8, Expand); in MSP430TargetLowering()
160 setOperationAction(ISD::UDIV, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1066 setOperationAction(ISD::UDIV, MVT::i32, Expand); in HexagonTargetLowering()
1069 setOperationAction(ISD::UDIV, MVT::i64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 121 setOperationAction(ISD::UDIV, MVT::i32, Expand); in MBlazeTargetLowering()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 167 setOperationAction(ISD::UDIV, MVT::i32, Expand); in MipsTargetLowering()
171 setOperationAction(ISD::UDIV, MVT::i64, Expand); in MipsTargetLowering()
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| D | MipsInstrInfo.td | 955 def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 325 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 148 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand); in addTypeForNEON()
531 setOperationAction(ISD::UDIV, MVT::v4i16, Custom); in ARMTargetLowering()
532 setOperationAction(ISD::UDIV, MVT::v8i8, Custom); in ARMTargetLowering()
640 setOperationAction(ISD::UDIV, MVT::i32, Expand); in ARMTargetLowering()
5183 case ISD::UDIV: return LowerUDIV(Op, DAG); in LowerOperation()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 342 setOperationAction(ISD::UDIV, VT, Expand); in PPCTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 354 setOperationAction(ISD::UDIV, VT, Expand); in X86TargetLowering()
719 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); in X86TargetLowering()
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