Searched refs:spsr (Results 1 – 11 of 11) sorted by relevance
| /external/qemu/target-arm/ |
| D | machine.c | 13 qemu_put_be32(f, env->spsr); in cpu_save()
129 env->spsr = qemu_get_be32(f); in cpu_load()
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| D | cpu.h | 89 uint32_t spsr; member
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| D | translate.c | 3490 static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) { in msr_mask() argument
3514 if (!spsr) in msr_mask()
3523 static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0) in gen_set_psr() argument
3526 if (spsr) { in gen_set_psr()
3531 tmp = load_cpu_field(spsr); in gen_set_psr()
3535 store_cpu_field(tmp, spsr); in gen_set_psr()
3545 static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val) in gen_set_psr_im() argument
3550 return gen_set_psr(s, mask, spsr, tmp); in gen_set_psr_im()
3558 tmp = load_cpu_field(spsr); in gen_exception_return()
6535 tmp = load_cpu_field(spsr); in disas_arm_insn()
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| D | helper.c | 683 env->banked_spsr[i] = env->spsr; in switch_mode()
688 env->spsr = env->banked_spsr[i]; in switch_mode()
948 env->spsr = cpsr_read(env); in do_interrupt()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 160 def SPSR : ARMReg<2, "spsr">;
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| D | ARMInstrThumb2.td | 3635 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []>,
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| D | ARMInstrInfo.td | 4666 "mrs", "\t$Rd, spsr", []> {
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 971 mrs r8, spsr
974 @ CHECK: mrs r8, spsr @ encoding: [0x00,0x80,0x4f,0xe1]
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| D | basic-thumb2-instructions.s | 1247 mrs r8, spsr
1251 @ CHECK: mrs r8, spsr @ encoding: [0xff,0xf3,0x00,0x88]
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 737 # CHECK: mrs r8, spsr
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| D | thumb2.txt | 992 # CHECK: mrs r8, spsr
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