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Searched refs:v4f32 (Results 1 – 25 of 62) sorted by relevance

123

/external/llvm/test/CodeGen/CellSPU/useful-harnesses/
Dvecoperations.c6 typedef float v4f32 __attribute__((ext_vector_type(4))); typedef
54 void print_v4f32(const char *str, v4f32 v) { in print_v4f32()
101 v4f32 v4f32_shuffle_1(v4f32 a) { in v4f32_shuffle_1()
102 v4f32 c2 = a.yzwx; in v4f32_shuffle_1()
106 v4f32 v4f32_shuffle_2(v4f32 a) { in v4f32_shuffle_2()
107 v4f32 c2 = a.zwxy; in v4f32_shuffle_2()
111 v4f32 v4f32_shuffle_3(v4f32 a) { in v4f32_shuffle_3()
112 v4f32 c2 = a.wxyz; in v4f32_shuffle_3()
116 v4f32 v4f32_shuffle_4(v4f32 a) { in v4f32_shuffle_4()
117 v4f32 c2 = a.xyzw; in v4f32_shuffle_4()
[all …]
/external/llvm/test/CodeGen/ARM/
D2011-11-29-128bitArithmetics.ll20 %1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %0)
25 declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readonly
52 %1 = call <4 x float> @llvm.cos.v4f32(<4 x float> %0)
57 declare <4 x float> @llvm.cos.v4f32(<4 x float>) nounwind readonly
83 %1 = call <4 x float> @llvm.exp.v4f32(<4 x float> %0)
88 declare <4 x float> @llvm.exp.v4f32(<4 x float>) nounwind readonly
114 %1 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %0)
119 declare <4 x float> @llvm.exp2.v4f32(<4 x float>) nounwind readonly
145 %1 = call <4 x float> @llvm.log10.v4f32(<4 x float> %0)
150 declare <4 x float> @llvm.log10.v4f32(<4 x float>) nounwind readonly
[all …]
Dspill-q.ll10 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
21 …%0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %vecptr, i32 1) nounwind ; <<4 x float>> [#use…
23 …%1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=…
25 …%2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=…
26 %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
28 %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
30 %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
32 %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
34 %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
36 %ld8 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
[all …]
Dvrec.ll31 %tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
39 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
55 %tmp3 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
60 declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
90 %tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
98 declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
114 %tmp3 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
119 declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
D2012-01-23-PostRA-LICM.ll32 %tmp16 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp11) nounwind
33 …%tmp17 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp16, <4 x float> %tmp11) noun…
35 …%tmp19 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp18, <4 x float> %tmp11) noun…
38 …%tmp22 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp21, <4 x float> undef) nounwi…
51 …%tmp34 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> undef, <4 x float> %tmp28) nounw…
73 …%tmp57 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp56, <4 x float> %tmp55) nounw…
97 declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
99 declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
101 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
Dvcvt.ll108 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
116 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
124 %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
132 %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
136 declare <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone
137 declare <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone
138 declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
139 declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
D2009-11-01-NeonMoves.ll23 …%8 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %7) nounwind ; <<4 x float>> [#uses…
25 …%10 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %9, <4 x float> %7) nounwind ; <<4…
38 declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
40 declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
D2010-05-21-BuildVector.ll39 tail call void @llvm.arm.neon.vst1.v4f32(i8* %20, <4 x float> %19, i32 1)
43 declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
D2012-01-24-RegSequenceLiveRange.ll55 tail call void @llvm.arm.neon.vst1.v4f32(i8* undef, <4 x float> %0, i32 4) nounwind
56 tail call void @llvm.arm.neon.vst1.v4f32(i8* undef, <4 x float> %2, i32 4) nounwind
64 declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
/external/llvm/lib/Target/CellSPU/
DSPUMathInstr.td60 // f32, v4f32 divide instruction sequence:
80 def Interpv4f32: CodeFrag<(FIv4f32 (v4f32 VECREG:$rB), (FRESTv4f32 (v4f32 VECREG:$rB)))>;
82 def DivEstv4f32: CodeFrag<(FMv4f32 (v4f32 VECREG:$rA), Interpv4f32.Fragment)>;
85 (v4f32 VECREG:$rB),
86 (v4f32 VECREG:$rA)),
92 def : Pat<(fdiv (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
95 (CGTIv4f32 (FNMSv4f32 (v4f32 VECREG:$rB),
97 (v4f32 VECREG:$rA)), -1))>;
DCellSDKIntrinsics.td345 [(set (v4f32 VECREG:$rT), (int_spu_si_fa (v4f32 VECREG:$rA),
346 (v4f32 VECREG:$rB)))]>;
351 [(set (v4f32 VECREG:$rT), (int_spu_si_fs (v4f32 VECREG:$rA),
352 (v4f32 VECREG:$rB)))]>;
357 [(set (v4f32 VECREG:$rT), (int_spu_si_fm (v4f32 VECREG:$rA),
358 (v4f32 VECREG:$rB)))]>;
363 [(set (v4f32 VECREG:$rT), (int_spu_si_fceq (v4f32 VECREG:$rA),
364 (v4f32 VECREG:$rB)))]>;
369 [(set (v4f32 VECREG:$rT), (int_spu_si_fcgt (v4f32 VECREG:$rA),
370 (v4f32 VECREG:$rB)))]>;
[all …]
DSPUCallingConv.td20 CCIfType<[i8,i16,i32,i64,i128,f32,f64,v16i8,v8i16,v4i32,v2i64,v4f32,v2f64],
37 v16i8, v8i16, v4i32, v4f32, v2i64, v2f64],
51 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
DSPUInstrInfo.td64 def v4f32: LoadDFormVec<v4f32>;
96 def v4f32: LoadAFormVec<v4f32>;
128 def v4f32: LoadXFormVec<v4f32>;
176 def v4f32: StoreDFormVec<v4f32>;
206 def v4f32: StoreAFormVec<v4f32>;
238 def v4f32: StoreXFormVec<v4f32>;
291 [(set (v4f32 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
295 [(set (v4f32 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
353 // TODO: Need v2f64, v4f32
632 def v4f32: AIFPVecInst<v4f32, v4i32SExt10Imm>;
[all …]
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-spill-q.ll10 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
21 %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %vecptr, i32 1) nounwind
23 …%1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=…
25 …%2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=…
26 %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
28 %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
30 %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
32 %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
34 %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
36 %ld8 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
[all …]
Dmachine-licm.ll62 %tmp2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %gep1, i32 1)
63 …%tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> <float 1.000000e+00, float 1.00000…
65 call void @llvm.arm.neon.vst1.v4f32(i8* %gep2, <4 x float> %tmp3, i32 1)
76 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
78 declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
80 declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
Dcrash.ll55 %vld1 = tail call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %p, i32 1)
57 tail call void @llvm.arm.neon.vst1.v4f32(i8* %p, <4 x float> %vld1, i32 1)
61 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
63 declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
/external/llvm/lib/Target/ARM/
DARMCallingConv.td28 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
47 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
61 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
73 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
118 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
128 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
143 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
155 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
/external/clang/test/CodeGen/
Dx86_64-arguments.c155 typedef float v4f32 __attribute__((__vector_size__(16))); typedef
156 v4f32 f25(v4f32 X) { in f25()
179 v4f32 v;
/external/llvm/include/llvm/CodeGen/
DValueTypes.h78 v4f32 = 31, // 4 x f32 enumerator
218 case v4f32: in getVectorElementType()
241 case v4f32: in getVectorNumElements()
290 case v4f32: in getSizeInBits()
383 if (NumElements == 4) return MVT::v4f32; in getVectorVT()
502 V==MVT::v2i64 || V==MVT::v4f32 || V==MVT::v2f64); in is128BitVector()
/external/llvm/lib/Target/X86/
DX86InstrSSE.td247 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
248 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
256 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
257 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
277 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
285 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
286 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
302 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
307 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
312 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
[all …]
DX86InstrFragmentsSIMD.td70 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
71 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
176 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
183 def ssmem : Operand<v4f32> {
202 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
247 (v4f32 (alignedload node:$ptr))>;
278 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
324 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
DX86CallingConv.td40 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
157 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
180 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
199 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
222 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
244 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
282 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
291 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
/external/llvm/lib/Target/PowerPC/
DPPCCallingConv.td28 CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>
46 CCIfType<[v16i8, v8i16, v4i32, v4f32],
55 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
90 CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToStack<16, 16>>
104 CCIfType<[v16i8, v8i16, v4i32, v4f32],
DPPCInstrAltivec.td534 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
535 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
536 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
537 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
538 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
539 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
540 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
541 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
610 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
614 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
[all …]
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp330 DecodeSHUFPMask(MVT::v4f32, MI->getOperand(MI->getNumOperands()-1).getImm(), in EmitAnyX86InstComments()
338 DecodeSHUFPMask(MVT::v4f32, MI->getOperand(MI->getNumOperands()-1).getImm(), in EmitAnyX86InstComments()
380 DecodeUNPCKLMask(MVT::v4f32, ShuffleMask); in EmitAnyX86InstComments()
387 DecodeUNPCKLMask(MVT::v4f32, ShuffleMask); in EmitAnyX86InstComments()
426 DecodeUNPCKHMask(MVT::v4f32, ShuffleMask); in EmitAnyX86InstComments()
433 DecodeUNPCKHMask(MVT::v4f32, ShuffleMask); in EmitAnyX86InstComments()
449 DecodePSHUFMask(MVT::v4f32, MI->getOperand(MI->getNumOperands()-1).getImm(), in EmitAnyX86InstComments()

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