1; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -verify-machineinstrs 2target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" 3target triple = "thumbv7-apple-darwin10" 4 5; This function would crash LiveIntervalAnalysis by creating a chain of 4 INSERT_SUBREGs of the same register. 6define arm_apcscc void @NEON_vst4q_u32(i32* nocapture %sp0, i32* nocapture %sp1, i32* nocapture %sp2, i32* nocapture %sp3, i32* %dp) nounwind { 7entry: 8 %0 = bitcast i32* %sp0 to <4 x i32>* ; <<4 x i32>*> [#uses=1] 9 %1 = load <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1] 10 %2 = bitcast i32* %sp1 to <4 x i32>* ; <<4 x i32>*> [#uses=1] 11 %3 = load <4 x i32>* %2, align 16 ; <<4 x i32>> [#uses=1] 12 %4 = bitcast i32* %sp2 to <4 x i32>* ; <<4 x i32>*> [#uses=1] 13 %5 = load <4 x i32>* %4, align 16 ; <<4 x i32>> [#uses=1] 14 %6 = bitcast i32* %sp3 to <4 x i32>* ; <<4 x i32>*> [#uses=1] 15 %7 = load <4 x i32>* %6, align 16 ; <<4 x i32>> [#uses=1] 16 %8 = bitcast i32* %dp to i8* ; <i8*> [#uses=1] 17 tail call void @llvm.arm.neon.vst4.v4i32(i8* %8, <4 x i32> %1, <4 x i32> %3, <4 x i32> %5, <4 x i32> %7, i32 1) 18 ret void 19} 20 21declare void @llvm.arm.neon.vst4.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind 22 23@sbuf = common global [16 x i32] zeroinitializer, align 16 ; <[16 x i32]*> [#uses=5] 24@dbuf = common global [16 x i32] zeroinitializer ; <[16 x i32]*> [#uses=2] 25 26; This function creates 4 chained INSERT_SUBREGS and then invokes the register scavenger. 27; The first INSERT_SUBREG needs an <undef> use operand for that to work. 28define arm_apcscc i32 @main() nounwind { 29bb.nph: 30 br label %bb 31 32bb: ; preds = %bb, %bb.nph 33 %0 = phi i32 [ 0, %bb.nph ], [ %1, %bb ] ; <i32> [#uses=4] 34 %scevgep = getelementptr [16 x i32]* @sbuf, i32 0, i32 %0 ; <i32*> [#uses=1] 35 %scevgep5 = getelementptr [16 x i32]* @dbuf, i32 0, i32 %0 ; <i32*> [#uses=1] 36 store i32 %0, i32* %scevgep, align 4 37 store i32 -1, i32* %scevgep5, align 4 38 %1 = add nsw i32 %0, 1 ; <i32> [#uses=2] 39 %exitcond = icmp eq i32 %1, 16 ; <i1> [#uses=1] 40 br i1 %exitcond, label %bb2, label %bb 41 42bb2: ; preds = %bb 43 %2 = load <4 x i32>* bitcast ([16 x i32]* @sbuf to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1] 44 %3 = load <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 4) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1] 45 %4 = load <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 8) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1] 46 %5 = load <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 12) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1] 47 tail call void @llvm.arm.neon.vst4.v4i32(i8* bitcast ([16 x i32]* @dbuf to i8*), <4 x i32> %2, <4 x i32> %3, <4 x i32> %4, <4 x i32> %5, i32 1) nounwind 48 ret i32 0 49} 50 51; PR12389 52; Make sure the DPair register class can spill. 53define void @pr12389(i8* %p) nounwind ssp { 54entry: 55 %vld1 = tail call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %p, i32 1) 56 tail call void asm sideeffect "", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q9},~{q10},~{q11},~{q12},~{q13},~{q14},~{q15}"() nounwind 57 tail call void @llvm.arm.neon.vst1.v4f32(i8* %p, <4 x float> %vld1, i32 1) 58 ret void 59} 60 61declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly 62 63declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind 64 65; <rdar://problem/11101911> 66; When an strd is expanded into two str instructions, make sure the first str 67; doesn't kill the base register. This can happen if the base register is the 68; same as the data register. 69%class = type { i8*, %class*, i32 } 70define void @f11101911(%class* %this, i32 %num) ssp align 2 { 71entry: 72 %p1 = getelementptr inbounds %class* %this, i32 0, i32 1 73 %p2 = getelementptr inbounds %class* %this, i32 0, i32 2 74 tail call void asm sideeffect "", "~{r1},~{r3},~{r5},~{r11},~{r13}"() nounwind 75 store %class* %this, %class** %p1, align 4 76 store i32 %num, i32* %p2, align 4 77 ret void 78} 79