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/external/openssl/crypto/rc4/
Drrc4.doc143 Key: 0x01 0x23 0x45 0x67 0x89 0xab 0xcd 0xef
144 Input: 0x01 0x23 0x45 0x67 0x89 0xab 0xcd 0xef
148 Key: 0x01 0x23 0x45 0x67 0x89 0xab 0xcd 0xef
158 Key: 0xef 0x01 0x23 0x45
163 Key: 0x01 0x23 0x45 0x67 0x89 0xab 0xcd 0xef
164 Input: 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01
165 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01
166 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01
167 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01
168 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01
[all …]
/external/icu4c/data/mappings/
Dlmb-excp.ucm19 <subchar> \x01\x3f
29 <U0027> \x01\x27 |0
30 <U005E> \x01\x23 |0
31 <U005E> \x01\x33 |3 # R5 compatibility
32 <U005E> \x01\x6D |3 # R5 compatibility
33 <U0060> \x01\x24 |0
34 <U0060> \x01\x34 |3 # R5 compatibility
35 <U007E> \x01\x21 |0
36 <U007E> \x01\x31 |3 # R5 compatibility
37 <U007E> \x01\x6C |3 # R5 compatibility
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dunpredictable-AI1cmp-arm.txt4 # CHECK: 0x01 0x10 0x50 0x03
5 0x01 0x10 0x50 0x03
8 # CHECK: 0x82 0x10 0x50 0x01
9 0x82 0x10 0x50 0x01
12 # CHECK: 0x02 0x10 0x50 0x01
13 0x02 0x10 0x50 0x01
16 # CHECK: 0x1f 0x01 0x52 0x01
17 0x1f 0x01 0x52 0x01
20 # CHECK: 0x10 0x11 0x52 0x01
21 0x10 0x11 0x52 0x01
[all …]
Dunpredictable-swp-arm.txt4 # CHECK: 0x9f 0x10 0x03 0x01
5 0x9f 0x10 0x03 0x01
8 # CHECK: 0x90 0xf0 0x03 0x01
9 0x90 0xf0 0x03 0x01
12 # CHECK: 0x90 0x1f 0x03 0x01
13 0x90 0x1f 0x03 0x01
16 # CHECK: 0x90 0x10 0x0f 0x01
17 0x90 0x10 0x0f 0x01
20 # CHECK: 0x90 0x10 0x01 0x01
21 0x90 0x10 0x01 0x01
[all …]
Dunpredictable-MRS-arm.txt4 # CHECK: 0x00 0xf0 0x0f 0x01
5 0x00 0xf0 0x0f 0x01
8 # CHECK: 0x00 0xf0 0x4f 0x01
9 0x00 0xf0 0x4f 0x01
12 # CHECK: 0x0f 0x0d 0x01 0x01
13 0x0f 0x0d 0x01 0x01
16 # CHECK: 0x0f 0x0d 0x40 0x01
17 0x0f 0x0d 0x40 0x01
Dunpredictable-MUL-arm.txt4 # CHECK: 0x93 0x12 0x01 0x00
5 0x93 0x12 0x01 0x00
8 # CHECK: 0x92 0x0f 0x01 0x00
9 0x92 0x0f 0x01 0x00
12 # CHECK: 0x9f 0x02 0x01 0x00
13 0x9f 0x02 0x01 0x00
16 # CHECK: 0x92 0x01 0x0f 0x00
17 0x92 0x01 0x0f 0x00
Dunpredictable-ADDREXT3-arm.txt4 # CHECK: 0xd1 0xf1 0x5f 0x01
5 0xd1 0xf1 0x5f 0x01
7 # CHECK: 0xf1 0xf1 0x5f 0x01
8 0xf1 0xf1 0x5f 0x01
10 # CHECK: 0xf1 0xf1 0x5f 0x01
11 0xf1 0xf1 0x5f 0x01
13 # CHECK: 0xd1 0xe1 0x4f 0x01
14 0xd1 0xe1 0x4f 0x01
/external/llvm/test/MC/Disassembler/MBlaze/
Dmblaze_fpu.txt8 0x58 0x01 0x10 0x00
11 0x58 0x01 0x10 0x80
14 0x58 0x01 0x11 0x00
17 0x58 0x01 0x11 0x80
20 0x58 0x01 0x03 0x80
23 0x58 0x01 0x03 0x00
26 0x58 0x01 0x02 0x80
29 0x58 0x01 0x12 0x00
32 0x58 0x01 0x12 0x10
35 0x58 0x01 0x12 0x20
[all …]
Dmblaze_pattern.txt8 0x80 0x01 0x14 0x00
11 0x8c 0x01 0x14 0x00
14 0x88 0x01 0x14 0x00
17 0x90 0x01 0x00 0xE0
/external/oprofile/events/i386/westmere/
Dunit_masks8 name:x01 type:mandatory default:0x01
9 0x01 No unit mask
18 name:arith type:bitmask default:0x01
19 0x01 cycles_div_busy Cycles the divider is busy
21 name:baclear type:bitmask default:0x01
22 0x01 clear BACLEAR asserted, regardless of cause
24 name:bpu_clears type:bitmask default:0x01
25 0x01 early Early Branch Prediction Unit clears
28 0x01 cond Conditional branch instructions executed
39 0x01 conditional Retired conditional branch instructions (Precise Event)
[all …]
Devents14 event:0x07 counters:0,1,2,3 um:x01 minimum:200000 name:PARTIAL_ADDRESS_ALIAS : False dependencies d…
17 event:0x0c counters:0,1,2,3 um:x01 minimum:200000 name:MEM_STORE_RETIRED : Retired stores that miss…
24 event:0x17 counters:0,1,2,3 um:x01 minimum:2000000 name:INST_QUEUE_WRITES : Instructions written to…
25 event:0x18 counters:0,1,2,3 um:x01 minimum:2000000 name:INST_DECODED : Instructions that must be de…
26 event:0x19 counters:0,1,2,3 um:x01 minimum:2000000 name:TWO_UOP_INSTS_DECODED : Two Uop instruction…
27 event:0x1e counters:0,1,2,3 um:x01 minimum:2000000 name:INST_QUEUE_WRITE_CYCLES : Cycles instructio…
28 event:0x20 counters:0,1,2,3 um:x01 minimum:2000000 name:LSD_OVERFLOW : Loops that can't stream from…
36 event:0x4c counters:0,1 um:x01 minimum:200000 name:LOAD_HIT_PRE : Load operations conflicting with …
40 event:0x52 counters:0,1 um:x01 minimum:2000000 name:L1D_CACHE_PREFETCH_LOCK_FB_HIT : L1D prefetch l…
43 event:0x6c counters:0,1,2,3 um:x01 minimum:2000000 name:IO_TRANSACTIONS : I/O transactions
[all …]
/external/icu4c/test/testdata/
Dtest3.ucm29 <U00c0> \x05+\x01\x02\x0d |0
30 <U00c0> \x05+\x01\x02\x0e |3
41 <U101234>+<U50005>+<U60006> \x07+\x00+\x01\x02\x0f+\x09 |0
42 <U101234>+<U50005> \x07+\x00+\x01\x02\x0e+\x05 |0
43 <U101234>+<U60006> \x07+\x00+\x01\x02\x0f+\x06 |0
44 <U101234>+<U70007> \x07+\x00+\x01\x02\x0f |1
50 <U00c4><U00c4><U101234><U0005> \x05+\x01\x02\x0c |0
53 <U23456> \x01\x02\x0a |0
54 <U000b> \x01\x02\x0b |0
55 #unassigned \x01\x02\x0c
[all …]
Dtest4.ucm46 <U23456> \x01\x02\x03\x0a |0
47 <U000b> \x01\x02\x03\x0b |0
48 #unassigned \x01\x02\x03\x0c
49 <U34567> \x01\x02\x03\x0d |3
50 <U000e> \x01\x02\x03\x0e |3
51 #unassigned \x01\x02\x03\x0f
59 <U30ab><U309a> \x01\x02\x03\x0a\x01\x02\x03\x0b\x01\x02\x03\x0c\x01\x02\x03\x0d\x01\x02\x03\x0e\x01…
/external/oprofile/events/i386/p4-ht/
Dunit_masks4 0x01 branch not-taken predicted
8 name:mispred_branch_retired type:bitmask default:0x01
9 0x01 retired instruction is non-bogus
10 # FIXME: 0 count nothing, 0xff count more than 0x01, docs says it's a bitmask:
12 name:bpu_fetch_request type:bitmask default:0x01
13 0x01 trace cache lookup miss
15 0x01 ITLB hit
22 0x01 load split completed, excluding UC/WC loads
36 0x01 read 2nd level cache hit shared
46 0x01 handle FP stack underflow
[all …]
/external/oprofile/events/i386/p4/
Dunit_masks4 0x01 branch not-taken predicted
8 name:mispred_branch_retired type:bitmask default:0x01
9 0x01 retired instruction is non-bogus
10 # FIXME: 0 count nothing, 0xff count more than 0x01, docs says it's a bitmask:
12 name:bpu_fetch_request type:bitmask default:0x01
13 0x01 trace cache lookup miss
15 0x01 ITLB hit
22 0x01 load split completed, excluding UC/WC loads
36 0x01 read 2nd level cache hit shared
46 0x01 bus request type bit 0
[all …]
/external/llvm/lib/Target/X86/
DX86InstrSVM.td19 def VMMCALL : I<0x01, MRM_D9, (outs), (ins), "vmmcall", []>, TB;
22 def STGI : I<0x01, MRM_DC, (outs), (ins), "stgi", []>, TB;
25 def CLGI : I<0x01, MRM_DD, (outs), (ins), "clgi", []>, TB;
29 def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|EAX}", []>, TB;
33 def VMRUN32 : I<0x01, MRM_D8, (outs), (ins),
36 def VMRUN64 : I<0x01, MRM_D8, (outs), (ins),
41 def VMLOAD32 : I<0x01, MRM_DA, (outs), (ins),
44 def VMLOAD64 : I<0x01, MRM_DA, (outs), (ins),
49 def VMSAVE32 : I<0x01, MRM_DB, (outs), (ins),
52 def VMSAVE64 : I<0x01, MRM_DB, (outs), (ins),
[all …]
/external/oprofile/events/i386/core_2/
Dunit_masks31 0x01 MES(I): Invalid
34 0x01 prefetch T1 instructions executed.
38 0x01 SIMD packed multiplies
46 0x01 float->MMX transitions
50 0x01 PREFETCHT0
59 0x01 SB_DRAIN_CYCLES Cycles while stores are blocked due to store buffer drain.
63 0x01 ANY Memory accesses that missed the DTLB.
67 name:memory_dis type:exclusive default:0x01
68 0x01 RESET Memory disambiguation reset cycles.
71 0x01 COUNT Number of page-walks executed.
[all …]
/external/oprofile/events/x86-64/family10/
Dunit_masks36 0x01 (I)nvalid cache state
43 0x01 Refill from northbridge
50 0x01 Add pipe ops excluding load ops and SSE move ops
58 0x01 ES register
66 0x01 x87 instructions
70 0x01 With low op in position 0
74 0x01 x87 reclass microfaults
79 0x01 DCT0 Page hit
86 0x01 DCT0 Page Table Overflow
89 0x01 DCT0 DIMM (chip select) turnaround
[all …]
/external/qemu-pc-bios/bochs/bios/
Dacpi-dsdt.hex16 0x01,0xA1,0x42,0x58,0x50,0x43,0x00,0x00, /* 00000008 "..BXPC.." */
18 0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */
20 0x5B,0x80,0x44,0x42,0x47,0x5F,0x01,0x0B, /* 00000028 "[.DBG_.." */
27 0x08,0x5F,0x55,0x49,0x44,0x01,0x08,0x5F, /* 00000060 "._UID.._" */
31 0xFF,0x01,0x4C,0x4E,0x4B,0x41,0x00,0x12, /* 00000080 "..LNKA.." */
35 0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x01, /* 000000A0 "........" */
37 0x0D,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x01, /* 000000B0 "........" */
39 0x0C,0xFF,0xFF,0x01,0x00,0x0A,0x02,0x4C, /* 000000C0 ".......L" */
41 0xFF,0xFF,0x01,0x00,0x0A,0x03,0x4C,0x4E, /* 000000D0 "......LN" */
45 0x00,0x01,0x4C,0x4E,0x4B,0x43,0x00,0x12, /* 000000F0 "..LNKC.." */
[all …]
Dacpi-dsdt.dsl22 0x01, // DSDT Compliance Revision
161 0x01, // Address Alignment
268 0x01, // Address Alignment
269 0x01, // Address Length
274 0x01, // Address Alignment
275 0x01, // Address Length
316 IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
356 Name (_UID, 0x01)
467 CreateWordField (PRR0, 0x01, TMP)
481 CreateWordField (Arg0, 0x01, TMP)
[all …]
/external/oprofile/events/i386/nehalem/
Dunit_masks6 name:sb_forward type:mandatory default:0x01
7 0x01 any Counts the number of store forwards
8 name:load_block type:bitmask default:0x01
9 0x01 std Counts the number of loads blocked by a preceding store with unknown data
11 name:sb_drain type:mandatory default:0x01
12 0x01 cycles Counts the cycles of store buffer drains
14 0x01 load Counts the number of misaligned load references
18 …0x01 not_sta This event counts the number of load operations delayed caused by preceding stores wh…
23 name:dtlb_load_misses type:bitmask default:0x01
24 0x01 any Counts all load misses that cause a page walk
[all …]
/external/oprofile/events/x86-64/hammer/
Dunit_masks19 0x01 (I)nvalid cache state
26 0x01 refill from system
33 0x01 Add pipe ops
40 0x01 ES register
48 0x01 Scrubber error
51 0x01 Load
55 0x01 x87 instructions
60 0x01 With low op in position 0
64 0x01 x87 reclass microfaults
69 0x01 Page hit
[all …]
/external/oprofile/events/x86-64/family11h/
Dunit_masks25 0x01 (I)nvalid cache state
32 0x01 refill from system
39 0x01 Add pipe ops
46 0x01 ES register
54 0x01 Scrubber error
57 0x01 Load
61 0x01 x87 instructions
66 0x01 With low op in position 0
70 0x01 x87 reclass microfaults
75 0x01 DCT0 Page hit
[all …]
/external/oprofile/events/i386/atom/
Dunit_masks9 name:simd_prefetch type:bitmask default:0x01
10 0x01 prefetcht0 Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed
22 0x01 s Floating point computational micro-ops executed
26 name:mul type:bitmask default:0x01
27 0x01 s Multiply operations executed
29 name:div type:bitmask default:0x01
30 0x01 s Divide operations executed
37 0x01 bus Bus cycles when core is not halted
57 name:simd_uop_type_exec type:bitmask default:0x01
58 0x01 s SIMD packed multiply microops executed
[all …]
/external/oprofile/events/i386/core/
Dunit_masks25 0x01 (I)nvalid cache state
35 0x01 prefetch T1
42 0x01 SSE Scalar-Single
46 0x01 MMX packed multiplies
55 0x01 float->MMX operations
58 0x01 Only load+Op micro-ops
62 0x01 Duration of cycles
65 0x01 PREFETCHT1

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