1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __ASM_ARCH_OMAP_FPGA_H 20 #define __ASM_ARCH_OMAP_FPGA_H 21 #define omap1510_fpga_init_irq() (0) 22 #define fpga_read(reg) __raw_readb(reg) 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #define fpga_write(val, reg) __raw_writeb(val, reg) 25 #define H2P2_DBG_FPGA_BASE 0xE8000000 26 #define H2P2_DBG_FPGA_SIZE SZ_4K 27 #define H2P2_DBG_FPGA_START 0x04000000 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) 30 #define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) 31 #define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) 32 #define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) 35 #define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) 36 #define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) 37 #define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 struct h2p2_dbg_fpga { 40 u16 smc91x[8]; 41 u16 fpga_rev; 42 u16 board_rev; 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 u16 gpio_outputs; 45 u16 leds; 46 u16 misc_inputs; 47 u16 lan_status; 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 u16 lan_reset; 50 u16 reserved0; 51 u16 ps2_data; 52 u16 ps2_ctrl; 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 }; 55 #define H2P2_DBG_FPGA_LED_GREEN (1 << 15) 56 #define H2P2_DBG_FPGA_LED_AMBER (1 << 14) 57 #define H2P2_DBG_FPGA_LED_RED (1 << 13) 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 #define H2P2_DBG_FPGA_LED_BLUE (1 << 12) 60 #define H2P2_DBG_FPGA_LOAD_METER (1 << 0) 61 #define H2P2_DBG_FPGA_LOAD_METER_SIZE 11 62 #define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1) 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 #define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0) 65 #define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1) 66 #define OMAP1510_FPGA_BASE 0xE8000000 67 #define OMAP1510_FPGA_SIZE SZ_4K 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 #define OMAP1510_FPGA_START 0x08000000 70 #define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0) 71 #define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1) 72 #define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2) 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 #define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3) 75 #define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4) 76 #define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5) 77 #define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6) 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 #define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7) 80 #define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8) 81 #define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9) 82 #define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa) 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 #define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb) 85 #define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc) 86 #define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe) 87 #define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf) 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 #define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14) 90 #define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15) 91 #define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16) 92 #define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18) 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 #define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100) 95 #define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101) 96 #define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102) 97 #define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204) 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 #define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205) 100 #define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206) 101 #define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207) 102 #define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208) 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 #define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209) 105 #define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a) 106 #define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b) 107 #define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c) 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 #define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d) 110 #define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e) 111 #define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210) 112 #define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300) 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 #define OMAP1510_FPGA_RESET_VALUE 0x42 115 #define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7) 116 #define OMAP1510_FPGA_PCR_COM2_EN (1 << 6) 117 #define OMAP1510_FPGA_PCR_COM1_EN (1 << 5) 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 #define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4) 120 #define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3) 121 #define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2) 122 #define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1) 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 #define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0) 125 #define OMAP1510_FPGA_HID_SCLK (1<<0) 126 #define OMAP1510_FPGA_HID_MOSI (1<<1) 127 #define OMAP1510_FPGA_HID_nSS (1<<2) 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 #define OMAP1510_FPGA_HID_nHSUS (1<<3) 130 #define OMAP1510_FPGA_HID_MISO (1<<4) 131 #define OMAP1510_FPGA_HID_ATN (1<<5) 132 #define OMAP1510_FPGA_HID_rsrvd (1<<6) 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 #define OMAP1510_FPGA_HID_RESETn (1<<7) 135 #define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13) 136 #define OMAP1510_IH_FPGA_BASE IH_BOARD_BASE 137 #define OMAP1510_INT_FPGA_ATN (OMAP1510_IH_FPGA_BASE + 0) 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 #define OMAP1510_INT_FPGA_ACK (OMAP1510_IH_FPGA_BASE + 1) 140 #define OMAP1510_INT_FPGA2 (OMAP1510_IH_FPGA_BASE + 2) 141 #define OMAP1510_INT_FPGA3 (OMAP1510_IH_FPGA_BASE + 3) 142 #define OMAP1510_INT_FPGA4 (OMAP1510_IH_FPGA_BASE + 4) 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 #define OMAP1510_INT_FPGA5 (OMAP1510_IH_FPGA_BASE + 5) 145 #define OMAP1510_INT_FPGA6 (OMAP1510_IH_FPGA_BASE + 6) 146 #define OMAP1510_INT_FPGA7 (OMAP1510_IH_FPGA_BASE + 7) 147 #define OMAP1510_INT_FPGA8 (OMAP1510_IH_FPGA_BASE + 8) 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 #define OMAP1510_INT_FPGA9 (OMAP1510_IH_FPGA_BASE + 9) 150 #define OMAP1510_INT_FPGA10 (OMAP1510_IH_FPGA_BASE + 10) 151 #define OMAP1510_INT_FPGA11 (OMAP1510_IH_FPGA_BASE + 11) 152 #define OMAP1510_INT_FPGA12 (OMAP1510_IH_FPGA_BASE + 12) 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 #define OMAP1510_INT_ETHER (OMAP1510_IH_FPGA_BASE + 13) 155 #define OMAP1510_INT_FPGAUART1 (OMAP1510_IH_FPGA_BASE + 14) 156 #define OMAP1510_INT_FPGAUART2 (OMAP1510_IH_FPGA_BASE + 15) 157 #define OMAP1510_INT_FPGA_TS (OMAP1510_IH_FPGA_BASE + 16) 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 #define OMAP1510_INT_FPGA17 (OMAP1510_IH_FPGA_BASE + 17) 160 #define OMAP1510_INT_FPGA_CAM (OMAP1510_IH_FPGA_BASE + 18) 161 #define OMAP1510_INT_FPGA_RTC_A (OMAP1510_IH_FPGA_BASE + 19) 162 #define OMAP1510_INT_FPGA_RTC_B (OMAP1510_IH_FPGA_BASE + 20) 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 #define OMAP1510_INT_FPGA_CD (OMAP1510_IH_FPGA_BASE + 21) 165 #define OMAP1510_INT_FPGA22 (OMAP1510_IH_FPGA_BASE + 22) 166 #define OMAP1510_INT_FPGA23 (OMAP1510_IH_FPGA_BASE + 23) 167 #endif 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169