1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Target-independent interfaces which we are implementing 15//===----------------------------------------------------------------------===// 16 17include "llvm/Target/Target.td" 18 19//===----------------------------------------------------------------------===// 20// ARM Subtarget state. 21// 22 23def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", 24 "Thumb mode">; 25 26//===----------------------------------------------------------------------===// 27// ARM Subtarget features. 28// 29 30def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 31 "Enable VFP2 instructions">; 32def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", 33 "Enable VFP3 instructions", 34 [FeatureVFP2]>; 35def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true", 36 "Enable VFP4 instructions", 37 [FeatureVFP3]>; 38def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 39 "Enable NEON instructions", 40 [FeatureVFP3]>; 41def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 42 "Enable Thumb2 instructions">; 43def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 44 "Does not support ARM mode execution">; 45def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 46 "Enable half-precision floating point">; 47def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true", 48 "Restrict VFP3 to 16 double registers">; 49def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true", 50 "Enable divide instructions">; 51def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true", 52 "Enable Thumb2 extract and pack instructions">; 53def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 54 "Has data barrier (dmb / dsb) instructions">; 55def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 56 "FP compare + branch is slow">; 57def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true", 58 "Floating point unit supports single precision only">; 59 60// Some processors have FP multiply-accumulate instructions that don't 61// play nicely with other VFP / NEON instructions, and it's generally better 62// to just not use them. 63def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 64 "Disable VFP / NEON MAC instructions">; 65 66// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 67def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 68 "HasVMLxForwarding", "true", 69 "Has multiplier accumulator forwarding">; 70 71// Some processors benefit from using NEON instructions for scalar 72// single-precision FP operations. 73def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", 74 "true", 75 "Use NEON for single precision FP">; 76 77// Disable 32-bit to 16-bit narrowing for experimentation. 78def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 79 "Prefer 32-bit Thumb instrs">; 80 81/// Some instructions update CPSR partially, which can add false dependency for 82/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 83/// mapped to a separate physical register. Avoid partial CPSR update for these 84/// processors. 85def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 86 "AvoidCPSRPartialUpdate", "true", 87 "Avoid CPSR partial update for OOO execution">; 88 89// Some processors perform return stack prediction. CodeGen should avoid issue 90// "normal" call instructions to callees which do not return. 91def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true", 92 "Has return address stack">; 93 94/// Some M architectures don't have the DSP extension (v7E-M vs. v7M) 95def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true", 96 "Supports v7 DSP instructions in Thumb2">; 97 98// Multiprocessing extension. 99def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 100 "Supports Multiprocessing extension">; 101 102// M-series ISA? 103def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true", 104 "Is microcontroller profile ('M' series)">; 105 106// ARM ISAs. 107def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 108 "Support ARM v4T instructions">; 109def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 110 "Support ARM v5T instructions", 111 [HasV4TOps]>; 112def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 113 "Support ARM v5TE, v5TEj, and v5TExp instructions", 114 [HasV5TOps]>; 115def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 116 "Support ARM v6 instructions", 117 [HasV5TEOps]>; 118def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 119 "Support ARM v6t2 instructions", 120 [HasV6Ops, FeatureThumb2]>; 121def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 122 "Support ARM v7 instructions", 123 [HasV6T2Ops]>; 124 125//===----------------------------------------------------------------------===// 126// ARM Processors supported. 127// 128 129include "ARMSchedule.td" 130 131// ARM processor families. 132def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 133 "Cortex-A8 ARM processors", 134 [FeatureSlowFPBrcc, FeatureNEONForFP, 135 FeatureHasSlowFPVMLx, FeatureVMLxForwarding, 136 FeatureT2XtPk]>; 137def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 138 "Cortex-A9 ARM processors", 139 [FeatureVMLxForwarding, 140 FeatureT2XtPk, FeatureFP16, 141 FeatureAvoidPartialCPSR]>; 142 143class ProcNoItin<string Name, list<SubtargetFeature> Features> 144 : Processor<Name, GenericItineraries, Features>; 145 146// V4 Processors. 147def : ProcNoItin<"generic", []>; 148def : ProcNoItin<"arm8", []>; 149def : ProcNoItin<"arm810", []>; 150def : ProcNoItin<"strongarm", []>; 151def : ProcNoItin<"strongarm110", []>; 152def : ProcNoItin<"strongarm1100", []>; 153def : ProcNoItin<"strongarm1110", []>; 154 155// V4T Processors. 156def : ProcNoItin<"arm7tdmi", [HasV4TOps]>; 157def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>; 158def : ProcNoItin<"arm710t", [HasV4TOps]>; 159def : ProcNoItin<"arm720t", [HasV4TOps]>; 160def : ProcNoItin<"arm9", [HasV4TOps]>; 161def : ProcNoItin<"arm9tdmi", [HasV4TOps]>; 162def : ProcNoItin<"arm920", [HasV4TOps]>; 163def : ProcNoItin<"arm920t", [HasV4TOps]>; 164def : ProcNoItin<"arm922t", [HasV4TOps]>; 165def : ProcNoItin<"arm940t", [HasV4TOps]>; 166def : ProcNoItin<"ep9312", [HasV4TOps]>; 167 168// V5T Processors. 169def : ProcNoItin<"arm10tdmi", [HasV5TOps]>; 170def : ProcNoItin<"arm1020t", [HasV5TOps]>; 171 172// V5TE Processors. 173def : ProcNoItin<"arm9e", [HasV5TEOps]>; 174def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>; 175def : ProcNoItin<"arm946e-s", [HasV5TEOps]>; 176def : ProcNoItin<"arm966e-s", [HasV5TEOps]>; 177def : ProcNoItin<"arm968e-s", [HasV5TEOps]>; 178def : ProcNoItin<"arm10e", [HasV5TEOps]>; 179def : ProcNoItin<"arm1020e", [HasV5TEOps]>; 180def : ProcNoItin<"arm1022e", [HasV5TEOps]>; 181def : ProcNoItin<"xscale", [HasV5TEOps]>; 182def : ProcNoItin<"iwmmxt", [HasV5TEOps]>; 183 184// V6 Processors. 185def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>; 186def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, 187 FeatureHasSlowFPVMLx]>; 188def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>; 189def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, 190 FeatureHasSlowFPVMLx]>; 191def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>; 192def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, 193 FeatureHasSlowFPVMLx]>; 194 195// V6M Processors. 196def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM, 197 FeatureDB, FeatureMClass]>; 198 199// V6T2 Processors. 200def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops, 201 FeatureDSPThumb2]>; 202def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2, 203 FeatureHasSlowFPVMLx, 204 FeatureDSPThumb2]>; 205 206// V7a Processors. 207def : Processor<"cortex-a8", CortexA8Itineraries, 208 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB, 209 FeatureDSPThumb2, FeatureHasRAS]>; 210def : Processor<"cortex-a9", CortexA9Itineraries, 211 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB, 212 FeatureDSPThumb2, FeatureHasRAS]>; 213def : Processor<"cortex-a9-mp", CortexA9Itineraries, 214 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB, 215 FeatureDSPThumb2, FeatureMP, 216 FeatureHasRAS]>; 217 218// V7M Processors. 219def : ProcNoItin<"cortex-m3", [HasV7Ops, 220 FeatureThumb2, FeatureNoARM, FeatureDB, 221 FeatureHWDiv, FeatureMClass]>; 222 223// V7EM Processors. 224def : ProcNoItin<"cortex-m4", [HasV7Ops, 225 FeatureThumb2, FeatureNoARM, FeatureDB, 226 FeatureHWDiv, FeatureDSPThumb2, 227 FeatureT2XtPk, FeatureVFP2, 228 FeatureVFPOnlySP, FeatureMClass]>; 229 230//===----------------------------------------------------------------------===// 231// Register File Description 232//===----------------------------------------------------------------------===// 233 234include "ARMRegisterInfo.td" 235 236include "ARMCallingConv.td" 237 238//===----------------------------------------------------------------------===// 239// Instruction Descriptions 240//===----------------------------------------------------------------------===// 241 242include "ARMInstrInfo.td" 243 244def ARMInstrInfo : InstrInfo; 245 246 247//===----------------------------------------------------------------------===// 248// Assembly printer 249//===----------------------------------------------------------------------===// 250// ARM Uses the MC printer for asm output, so make sure the TableGen 251// AsmWriter bits get associated with the correct class. 252def ARMAsmWriter : AsmWriter { 253 string AsmWriterClassName = "InstPrinter"; 254 bit isMCAsmWriter = 1; 255} 256 257//===----------------------------------------------------------------------===// 258// Declare the target which we are implementing 259//===----------------------------------------------------------------------===// 260 261def ARM : Target { 262 // Pull in Instruction Info: 263 let InstructionSet = ARMInstrInfo; 264 265 let AssemblyWriters = [ARMAsmWriter]; 266} 267