1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef Hexagon_ISELLOWERING_H 16 #define Hexagon_ISELLOWERING_H 17 18 #include "Hexagon.h" 19 #include "llvm/Target/TargetLowering.h" 20 #include "llvm/CallingConv.h" 21 #include "llvm/CodeGen/CallingConvLower.h" 22 23 namespace llvm { 24 namespace HexagonISD { 25 enum { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 28 CONST32, 29 CONST32_GP, // For marking data present in GP. 30 SETCC, 31 ADJDYNALLOC, 32 ARGEXTEND, 33 34 CMPICC, // Compare two GPR operands, set icc. 35 CMPFCC, // Compare two FP operands, set fcc. 36 BRICC, // Branch to dest on icc condition 37 BRFCC, // Branch to dest on fcc condition 38 SELECT_ICC, // Select between two values using the current ICC flags. 39 SELECT_FCC, // Select between two values using the current FCC flags. 40 41 Hi, Lo, // Hi/Lo operations, typically on a global address. 42 43 FTOI, // FP to Int within a FP register. 44 ITOF, // Int to FP within a FP register. 45 46 CALL, // A call instruction. 47 RET_FLAG, // Return with a flag operand. 48 BR_JT, // Jump table. 49 BARRIER, // Memory barrier. 50 WrapperJT, 51 TC_RETURN 52 }; 53 } 54 55 class HexagonTargetLowering : public TargetLowering { 56 int VarArgsFrameOffset; // Frame offset to start of varargs area. 57 58 bool CanReturnSmallStruct(const Function* CalleeFn, 59 unsigned& RetSize) const; 60 61 public: 62 HexagonTargetMachine &TM; 63 explicit HexagonTargetLowering(HexagonTargetMachine &targetmachine); 64 65 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 66 /// for tail call optimization. Targets which want to do tail call 67 /// optimization should implement this function. 68 bool 69 IsEligibleForTailCallOptimization(SDValue Callee, 70 CallingConv::ID CalleeCC, 71 bool isVarArg, 72 bool isCalleeStructRet, 73 bool isCallerStructRet, 74 const 75 SmallVectorImpl<ISD::OutputArg> &Outs, 76 const SmallVectorImpl<SDValue> &OutVals, 77 const SmallVectorImpl<ISD::InputArg> &Ins, 78 SelectionDAG& DAG) const; 79 80 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const; 81 virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 82 83 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 84 85 virtual const char *getTargetNodeName(unsigned Opcode) const; 86 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 87 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 88 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; 89 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const; 90 SDValue LowerFormalArguments(SDValue Chain, 91 CallingConv::ID CallConv, bool isVarArg, 92 const SmallVectorImpl<ISD::InputArg> &Ins, 93 DebugLoc dl, SelectionDAG &DAG, 94 SmallVectorImpl<SDValue> &InVals) const; 95 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const; 96 97 SDValue LowerCall(SDValue Chain, SDValue Callee, 98 CallingConv::ID CallConv, bool isVarArg, 99 bool doesNotRet, bool &isTailCall, 100 const SmallVectorImpl<ISD::OutputArg> &Outs, 101 const SmallVectorImpl<SDValue> &OutVals, 102 const SmallVectorImpl<ISD::InputArg> &Ins, 103 DebugLoc dl, SelectionDAG &DAG, 104 SmallVectorImpl<SDValue> &InVals) const; 105 106 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 107 CallingConv::ID CallConv, bool isVarArg, 108 const SmallVectorImpl<ISD::InputArg> &Ins, 109 DebugLoc dl, SelectionDAG &DAG, 110 SmallVectorImpl<SDValue> &InVals, 111 const SmallVectorImpl<SDValue> &OutVals, 112 SDValue Callee) const; 113 114 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 115 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 116 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const; 117 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 118 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 119 120 SDValue LowerReturn(SDValue Chain, 121 CallingConv::ID CallConv, bool isVarArg, 122 const SmallVectorImpl<ISD::OutputArg> &Outs, 123 const SmallVectorImpl<SDValue> &OutVals, 124 DebugLoc dl, SelectionDAG &DAG) const; 125 126 virtual MachineBasicBlock 127 *EmitInstrWithCustomInserter(MachineInstr *MI, 128 MachineBasicBlock *BB) const; 129 130 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; getSetCCResultType(EVT VT)131 virtual EVT getSetCCResultType(EVT VT) const { 132 return MVT::i1; 133 } 134 135 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 136 SDValue &Base, SDValue &Offset, 137 ISD::MemIndexedMode &AM, 138 SelectionDAG &DAG) const; 139 140 std::pair<unsigned, const TargetRegisterClass*> 141 getRegForInlineAsmConstraint(const std::string &Constraint, 142 EVT VT) const; 143 144 // Intrinsics 145 virtual SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, 146 SelectionDAG &DAG) const; 147 /// isLegalAddressingMode - Return true if the addressing mode represented 148 /// by AM is legal for this target, for a load/store of the specified type. 149 /// The type may be VoidTy, in which case only return true if the addressing 150 /// mode is legal for a load/store of any legal type. 151 /// TODO: Handle pre/postinc as well. 152 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 153 154 /// isLegalICmpImmediate - Return true if the specified immediate is legal 155 /// icmp immediate, that is the target has icmp instructions which can 156 /// compare a register against the immediate without having to materialize 157 /// the immediate into a register. 158 virtual bool isLegalICmpImmediate(int64_t Imm) const; 159 }; 160 } // end namespace llvm 161 162 #endif // Hexagon_ISELLOWERING_H 163