1//==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Hexagon Intruction Flags + 12// 13// *** Must match HexagonBaseInfo.h *** 14//===----------------------------------------------------------------------===// 15 16 17//===----------------------------------------------------------------------===// 18// Intruction Class Declaration + 19//===----------------------------------------------------------------------===// 20 21class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, 22 string cstr, InstrItinClass itin> : Instruction { 23 field bits<32> Inst; 24 25 let Namespace = "Hexagon"; 26 27 dag OutOperandList = outs; 28 dag InOperandList = ins; 29 let AsmString = asmstr; 30 let Pattern = pattern; 31 let Constraints = cstr; 32 let Itinerary = itin; 33 34 // *** The code below must match HexagonBaseInfo.h *** 35 36 // Predicated instructions. 37 bits<1> isPredicated = 0; 38 let TSFlags{1} = isPredicated; 39 40 // *** The code above must match HexagonBaseInfo.h *** 41} 42 43//===----------------------------------------------------------------------===// 44// Intruction Classes Definitions + 45//===----------------------------------------------------------------------===// 46 47// LD Instruction Class in V2/V3/V4. 48// Definition of the instruction class NOT CHANGED. 49class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern> 50 : InstHexagon<outs, ins, asmstr, pattern, "", LD> { 51 bits<5> rd; 52 bits<5> rs; 53 bits<13> imm13; 54} 55 56// LD Instruction Class in V2/V3/V4. 57// Definition of the instruction class NOT CHANGED. 58class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern, 59 string cstr> 60 : InstHexagon<outs, ins, asmstr, pattern, cstr, LD> { 61 bits<5> rd; 62 bits<5> rs; 63 bits<5> rt; 64 bits<13> imm13; 65} 66 67// ST Instruction Class in V2/V3 can take SLOT0 only. 68// ST Instruction Class in V4 can take SLOT0 & SLOT1. 69// Definition of the instruction class CHANGED from V2/V3 to V4. 70class STInst<dag outs, dag ins, string asmstr, list<dag> pattern> 71 : InstHexagon<outs, ins, asmstr, pattern, "", ST> { 72 bits<5> rd; 73 bits<5> rs; 74 bits<13> imm13; 75} 76 77// ST Instruction Class in V2/V3 can take SLOT0 only. 78// ST Instruction Class in V4 can take SLOT0 & SLOT1. 79// Definition of the instruction class CHANGED from V2/V3 to V4. 80class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern, 81 string cstr> 82 : InstHexagon<outs, ins, asmstr, pattern, cstr, ST> { 83 bits<5> rd; 84 bits<5> rs; 85 bits<5> rt; 86 bits<13> imm13; 87} 88 89// ALU32 Instruction Class in V2/V3/V4. 90// Definition of the instruction class NOT CHANGED. 91class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern> 92 : InstHexagon<outs, ins, asmstr, pattern, "", ALU32> { 93 bits<5> rd; 94 bits<5> rs; 95 bits<5> rt; 96 bits<16> imm16; 97 bits<16> imm16_2; 98} 99 100// ALU64 Instruction Class in V2/V3. 101// XTYPE Instruction Class in V4. 102// Definition of the instruction class NOT CHANGED. 103// Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4. 104class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern> 105 : InstHexagon<outs, ins, asmstr, pattern, "", ALU64> { 106 bits<5> rd; 107 bits<5> rs; 108 bits<5> rt; 109 bits<16> imm16; 110 bits<16> imm16_2; 111} 112 113// M Instruction Class in V2/V3. 114// XTYPE Instruction Class in V4. 115// Definition of the instruction class NOT CHANGED. 116// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. 117class MInst<dag outs, dag ins, string asmstr, list<dag> pattern> 118 : InstHexagon<outs, ins, asmstr, pattern, "", M> { 119 bits<5> rd; 120 bits<5> rs; 121 bits<5> rt; 122} 123 124// M Instruction Class in V2/V3. 125// XTYPE Instruction Class in V4. 126// Definition of the instruction class NOT CHANGED. 127// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. 128class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern, 129 string cstr> 130 : InstHexagon<outs, ins, asmstr, pattern, cstr, M> { 131 bits<5> rd; 132 bits<5> rs; 133 bits<5> rt; 134} 135 136// S Instruction Class in V2/V3. 137// XTYPE Instruction Class in V4. 138// Definition of the instruction class NOT CHANGED. 139// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. 140class SInst<dag outs, dag ins, string asmstr, list<dag> pattern> 141//: InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, M)> { 142 : InstHexagon<outs, ins, asmstr, pattern, "", S> { 143// : InstHexagon<outs, ins, asmstr, pattern, "", S> { 144 bits<5> rd; 145 bits<5> rs; 146 bits<5> rt; 147} 148 149// S Instruction Class in V2/V3. 150// XTYPE Instruction Class in V4. 151// Definition of the instruction class NOT CHANGED. 152// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. 153class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern, 154 string cstr> 155 : InstHexagon<outs, ins, asmstr, pattern, cstr, S> { 156// : InstHexagon<outs, ins, asmstr, pattern, cstr, S> { 157// : InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, S)> { 158 bits<5> rd; 159 bits<5> rs; 160 bits<5> rt; 161} 162 163// J Instruction Class in V2/V3/V4. 164// Definition of the instruction class NOT CHANGED. 165class JType<dag outs, dag ins, string asmstr, list<dag> pattern> 166 : InstHexagon<outs, ins, asmstr, pattern, "", J> { 167 bits<16> imm16; 168} 169 170// JR Instruction Class in V2/V3/V4. 171// Definition of the instruction class NOT CHANGED. 172class JRType<dag outs, dag ins, string asmstr, list<dag> pattern> 173 : InstHexagon<outs, ins, asmstr, pattern, "", JR> { 174 bits<5> rs; 175 bits<5> pu; // Predicate register 176} 177 178// CR Instruction Class in V2/V3/V4. 179// Definition of the instruction class NOT CHANGED. 180class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern> 181 : InstHexagon<outs, ins, asmstr, pattern, "", CR> { 182 bits<5> rs; 183 bits<10> imm10; 184} 185 186 187class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 188 : InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO>; 189 190 191//===----------------------------------------------------------------------===// 192// Intruction Classes Definitions - 193//===----------------------------------------------------------------------===// 194 195 196// 197// ALU32 patterns 198//. 199class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern> 200 : ALU32Type<outs, ins, asmstr, pattern> { 201} 202 203class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern> 204 : ALU32Type<outs, ins, asmstr, pattern> { 205 let rt{0-4} = 0; 206} 207 208class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern> 209 : ALU32Type<outs, ins, asmstr, pattern> { 210 let rt{0-4} = 0; 211} 212 213class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern> 214 : ALU32Type<outs, ins, asmstr, pattern> { 215 let rt{0-4} = 0; 216} 217 218// 219// ALU64 patterns. 220// 221class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern> 222 : ALU64Type<outs, ins, asmstr, pattern> { 223} 224 225// J Type Instructions. 226class JInst<dag outs, dag ins, string asmstr, list<dag> pattern> 227 : JType<outs, ins, asmstr, pattern> { 228} 229 230// JR type Instructions. 231class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern> 232 : JRType<outs, ins, asmstr, pattern> { 233} 234 235 236// Post increment ST Instruction. 237class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr> 238 : STInstPost<outs, ins, asmstr, pattern, cstr> { 239 let rt{0-4} = 0; 240} 241 242// Post increment LD Instruction. 243class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr> 244 : LDInstPost<outs, ins, asmstr, pattern, cstr> { 245 let rt{0-4} = 0; 246} 247 248//===----------------------------------------------------------------------===// 249// V4 Instruction Format Definitions + 250//===----------------------------------------------------------------------===// 251 252include "HexagonInstrFormatsV4.td" 253 254//===----------------------------------------------------------------------===// 255// V4 Instruction Format Definitions + 256//===----------------------------------------------------------------------===// 257