1//==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Hexagon V4 instruction classes in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14// 15// NV type instructions. 16// 17class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern> 18 : InstHexagon<outs, ins, asmstr, pattern, "", NV_V4> { 19 bits<5> rd; 20 bits<5> rs; 21 bits<13> imm13; 22} 23 24// Definition of Post increment new value store. 25class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern, 26 string cstr> 27 : InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4> { 28 bits<5> rd; 29 bits<5> rs; 30 bits<5> rt; 31 bits<13> imm13; 32} 33 34// Post increment ST Instruction. 35class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern, 36 string cstr> 37 : NVInstPost_V4<outs, ins, asmstr, pattern, cstr> { 38 let rt{0-4} = 0; 39} 40 41class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern> 42 : InstHexagon<outs, ins, asmstr, pattern, "", MEM_V4> { 43 bits<5> rd; 44 bits<5> rs; 45 bits<6> imm6; 46} 47