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1//=-HexagonScheduleV4.td - HexagonV4 Scheduling Definitions --*- tablegen -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10// There are four SLOTS (four parallel pipelines) in Hexagon V4 machine.
11// This file describes that machine information.
12
13//
14//    |===========|==================================================|
15//    | PIPELINE  |              Instruction Classes                 |
16//    |===========|==================================================|
17//    | SLOT0     |  LD       ST    ALU32     MEMOP     NV    SYSTEM |
18//    |-----------|--------------------------------------------------|
19//    | SLOT1     |  LD       ST    ALU32                            |
20//    |-----------|--------------------------------------------------|
21//    | SLOT2     |  XTYPE          ALU32     J         JR           |
22//    |-----------|--------------------------------------------------|
23//    | SLOT3     |  XTYPE          ALU32     J         CR           |
24//    |===========|==================================================|
25
26
27// Functional Units.
28def SLOT0       : FuncUnit;
29def SLOT1       : FuncUnit;
30def SLOT2       : FuncUnit;
31def SLOT3       : FuncUnit;
32
33// Itinerary classes.
34def NV_V4       : InstrItinClass;
35def MEM_V4      : InstrItinClass;
36// ALU64/M/S Instruction classes of V2 are collectively knownn as XTYPE in V4.
37
38def HexagonItinerariesV4 : ProcessorItineraries<
39                    [SLOT0, SLOT1, SLOT2, SLOT3], [], [
40  InstrItinData<LD            , [InstrStage<1,  [SLOT0, SLOT1]>]>,
41  InstrItinData<ST            , [InstrStage<1,  [SLOT0, SLOT1]>]>,
42  InstrItinData<ALU32         , [InstrStage<1,  [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
43  InstrItinData<NV_V4         , [InstrStage<1,  [SLOT0]>]>,
44  InstrItinData<MEM_V4        , [InstrStage<1,  [SLOT0]>]>,
45  InstrItinData<J             , [InstrStage<1,  [SLOT2, SLOT3]>]>,
46  InstrItinData<JR            , [InstrStage<1,  [SLOT2]>]>,
47  InstrItinData<CR            , [InstrStage<1,  [SLOT3]>]>,
48  InstrItinData<PSEUDO        , [InstrStage<1,  [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
49  InstrItinData<ALU64         , [InstrStage<1,  [SLOT2, SLOT3]>]>,
50  InstrItinData<M             , [InstrStage<1,  [SLOT2, SLOT3]>]>,
51  InstrItinData<S             , [InstrStage<1,  [SLOT2, SLOT3]>]>
52]>;
53
54//===----------------------------------------------------------------------===//
55// Hexagon V4 Resource Definitions -
56//===----------------------------------------------------------------------===//
57