1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This is the top level entry point for the PowerPC target. 11// 12//===----------------------------------------------------------------------===// 13 14// Get the target-independent interfaces which we are implementing. 15// 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// PowerPC Subtarget features. 20// 21 22//===----------------------------------------------------------------------===// 23// CPU Directives // 24//===----------------------------------------------------------------------===// 25 26def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">; 27def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">; 28def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">; 29def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 30def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 31def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 32def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">; 33def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">; 34def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">; 35def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">; 36def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">; 37def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">; 38 39def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 40 "Enable 64-bit instructions">; 41def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 42 "Enable 64-bit registers usage for ppc32 [beta]">; 43def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 44 "Enable Altivec instructions">; 45def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true", 46 "Enable GPUL instructions">; 47def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 48 "Enable the fsqrt instruction">; 49def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 50 "Enable the stfiwx instruction">; 51def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 52 "Enable Book E instructions">; 53 54//===----------------------------------------------------------------------===// 55// Register File Description 56//===----------------------------------------------------------------------===// 57 58include "PPCRegisterInfo.td" 59include "PPCSchedule.td" 60include "PPCInstrInfo.td" 61 62//===----------------------------------------------------------------------===// 63// PowerPC processors supported. 64// 65 66def : Processor<"generic", G3Itineraries, [Directive32]>; 67def : Processor<"440", PPC440Itineraries, [Directive440, FeatureBookE]>; 68def : Processor<"450", PPC440Itineraries, [Directive440, FeatureBookE]>; 69def : Processor<"601", G3Itineraries, [Directive601]>; 70def : Processor<"602", G3Itineraries, [Directive602]>; 71def : Processor<"603", G3Itineraries, [Directive603]>; 72def : Processor<"603e", G3Itineraries, [Directive603]>; 73def : Processor<"603ev", G3Itineraries, [Directive603]>; 74def : Processor<"604", G3Itineraries, [Directive604]>; 75def : Processor<"604e", G3Itineraries, [Directive604]>; 76def : Processor<"620", G3Itineraries, [Directive620]>; 77def : Processor<"g3", G3Itineraries, [Directive7400]>; 78def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>; 79def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>; 80def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>; 81def : Processor<"g4+", G4PlusItineraries, [Directive750, FeatureAltivec]>; 82def : Processor<"750", G4Itineraries, [Directive750, FeatureAltivec]>; 83def : Processor<"970", G5Itineraries, 84 [Directive970, FeatureAltivec, 85 FeatureGPUL, FeatureFSqrt, FeatureSTFIWX, 86 Feature64Bit /*, Feature64BitRegs */]>; 87def : Processor<"g5", G5Itineraries, 88 [Directive970, FeatureAltivec, 89 FeatureGPUL, FeatureFSqrt, FeatureSTFIWX, 90 Feature64Bit /*, Feature64BitRegs */]>; 91def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE, 92 FeatureFSqrt, FeatureSTFIWX, 93 Feature64Bit 94 /*, Feature64BitRegs */]>; 95def : Processor<"ppc", G3Itineraries, [Directive32]>; 96def : Processor<"ppc64", G5Itineraries, 97 [Directive64, FeatureAltivec, 98 FeatureGPUL, FeatureFSqrt, FeatureSTFIWX, 99 Feature64Bit /*, Feature64BitRegs */]>; 100 101 102//===----------------------------------------------------------------------===// 103// Calling Conventions 104//===----------------------------------------------------------------------===// 105 106include "PPCCallingConv.td" 107 108def PPCInstrInfo : InstrInfo { 109 let isLittleEndianEncoding = 1; 110} 111 112def PPCAsmWriter : AsmWriter { 113 string AsmWriterClassName = "InstPrinter"; 114 bit isMCAsmWriter = 1; 115} 116 117def PPC : Target { 118 // Information about the instructions. 119 let InstructionSet = PPCInstrInfo; 120 121 let AssemblyWriters = [PPCAsmWriter]; 122} 123