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1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
17 
18 #include "PPC.h"
19 #include "PPCSubtarget.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 
23 namespace llvm {
24   namespace PPCISD {
25     enum NodeType {
26       // Start the numbering where the builtin ops and target ops leave off.
27       FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 
29       /// FSEL - Traditional three-operand fsel node.
30       ///
31       FSEL,
32 
33       /// FCFID - The FCFID instruction, taking an f64 operand and producing
34       /// and f64 value containing the FP representation of the integer that
35       /// was temporarily in the f64 operand.
36       FCFID,
37 
38       /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
39       /// operand, producing an f64 value containing the integer representation
40       /// of that FP value.
41       FCTIDZ, FCTIWZ,
42 
43       /// STFIWX - The STFIWX instruction.  The first operand is an input token
44       /// chain, then an f64 value to store, then an address to store it to.
45       STFIWX,
46 
47       // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
48       // three v4f32 operands and producing a v4f32 result.
49       VMADDFP, VNMSUBFP,
50 
51       /// VPERM - The PPC VPERM Instruction.
52       ///
53       VPERM,
54 
55       /// Hi/Lo - These represent the high and low 16-bit parts of a global
56       /// address respectively.  These nodes have two operands, the first of
57       /// which must be a TargetGlobalAddress, and the second of which must be a
58       /// Constant.  Selected naively, these turn into 'lis G+C' and 'li G+C',
59       /// though these are usually folded into other nodes.
60       Hi, Lo,
61 
62       TOC_ENTRY,
63 
64       /// The following three target-specific nodes are used for calls through
65       /// function pointers in the 64-bit SVR4 ABI.
66 
67       /// Restore the TOC from the TOC save area of the current stack frame.
68       /// This is basically a hard coded load instruction which additionally
69       /// takes/produces a flag.
70       TOC_RESTORE,
71 
72       /// Like a regular LOAD but additionally taking/producing a flag.
73       LOAD,
74 
75       /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
76       /// a hard coded load instruction.
77       LOAD_TOC,
78 
79       /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
80       /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
81       /// compute an allocation on the stack.
82       DYNALLOC,
83 
84       /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
85       /// at function entry, used for PIC code.
86       GlobalBaseReg,
87 
88       /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
89       /// shift amounts.  These nodes are generated by the multi-precision shift
90       /// code.
91       SRL, SRA, SHL,
92 
93       /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
94       /// registers.
95       EXTSW_32,
96 
97       /// CALL - A direct function call.
98       /// CALL_NOP_SVR4 is a call with the special  NOP which follows 64-bit
99       /// SVR4 calls.
100       CALL_Darwin, CALL_SVR4, CALL_NOP_SVR4,
101 
102       /// NOP - Special NOP which follows 64-bit SVR4 calls.
103       NOP,
104 
105       /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
106       /// MTCTR instruction.
107       MTCTR,
108 
109       /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
110       /// BCTRL instruction.
111       BCTRL_Darwin, BCTRL_SVR4,
112 
113       /// Return with a flag operand, matched by 'blr'
114       RET_FLAG,
115 
116       /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCRpseud/MFOCRF
117       /// instructions.  This copies the bits corresponding to the specified
118       /// CRREG into the resultant GPR.  Bits corresponding to other CR regs
119       /// are undefined.
120       MFCR,
121 
122       /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
123       /// instructions.  For lack of better number, we use the opcode number
124       /// encoding for the OPC field to identify the compare.  For example, 838
125       /// is VCMPGTSH.
126       VCMP,
127 
128       /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
129       /// altivec VCMP*o instructions.  For lack of better number, we use the
130       /// opcode number encoding for the OPC field to identify the compare.  For
131       /// example, 838 is VCMPGTSH.
132       VCMPo,
133 
134       /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
135       /// corresponds to the COND_BRANCH pseudo instruction.  CRRC is the
136       /// condition register to branch on, OPC is the branch opcode to use (e.g.
137       /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
138       /// an optional input flag argument.
139       COND_BRANCH,
140 
141       // The following 5 instructions are used only as part of the
142       // long double-to-int conversion sequence.
143 
144       /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the
145       /// register.
146       MFFS,
147 
148       /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.
149       MTFSB0,
150 
151       /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.
152       MTFSB1,
153 
154       /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with
155       /// rounding towards zero.  It has flags added so it won't move past the
156       /// FPSCR-setting instructions.
157       FADDRTZ,
158 
159       /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
160       MTFSF,
161 
162       /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
163       /// reserve indexed. This is used to implement atomic operations.
164       LARX,
165 
166       /// STCX = This corresponds to PPC stcx. instrcution: store conditional
167       /// indexed. This is used to implement atomic operations.
168       STCX,
169 
170       /// TC_RETURN - A tail call return.
171       ///   operand #0 chain
172       ///   operand #1 callee (register or absolute)
173       ///   operand #2 stack adjustment
174       ///   operand #3 optional in flag
175       TC_RETURN,
176 
177       /// STD_32 - This is the STD instruction for use with "32-bit" registers.
178       STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE,
179 
180       /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
181       /// byte-swapping store instruction.  It byte-swaps the low "Type" bits of
182       /// the GPRC input, then stores it through Ptr.  Type can be either i16 or
183       /// i32.
184       STBRX,
185 
186       /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
187       /// byte-swapping load instruction.  It loads "Type" bits, byte swaps it,
188       /// then puts it in the bottom bits of the GPRC.  TYPE can be either i16
189       /// or i32.
190       LBRX
191     };
192   }
193 
194   /// Define some predicates that are used for node matching.
195   namespace PPC {
196     /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
197     /// VPKUHUM instruction.
198     bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
199 
200     /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
201     /// VPKUWUM instruction.
202     bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
203 
204     /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
205     /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
206     bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
207                             bool isUnary);
208 
209     /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
210     /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
211     bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
212                             bool isUnary);
213 
214     /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
215     /// amount, otherwise return -1.
216     int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
217 
218     /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
219     /// specifies a splat of a single element that is suitable for input to
220     /// VSPLTB/VSPLTH/VSPLTW.
221     bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
222 
223     /// isAllNegativeZeroVector - Returns true if all elements of build_vector
224     /// are -0.0.
225     bool isAllNegativeZeroVector(SDNode *N);
226 
227     /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
228     /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
229     unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
230 
231     /// get_VSPLTI_elt - If this is a build_vector of constants which can be
232     /// formed by using a vspltis[bhw] instruction of the specified element
233     /// size, return the constant being splatted.  The ByteSize field indicates
234     /// the number of bytes of each element [124] -> [bhw].
235     SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
236   }
237 
238   class PPCTargetLowering : public TargetLowering {
239     const PPCSubtarget &PPCSubTarget;
240 
241   public:
242     explicit PPCTargetLowering(PPCTargetMachine &TM);
243 
244     /// getTargetNodeName() - This method returns the name of a target specific
245     /// DAG node.
246     virtual const char *getTargetNodeName(unsigned Opcode) const;
247 
getShiftAmountTy(EVT LHSTy)248     virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
249 
250     /// getSetCCResultType - Return the ISD::SETCC ValueType
251     virtual EVT getSetCCResultType(EVT VT) const;
252 
253     /// getPreIndexedAddressParts - returns true by value, base pointer and
254     /// offset pointer and addressing mode by reference if the node's address
255     /// can be legally represented as pre-indexed load / store address.
256     virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
257                                            SDValue &Offset,
258                                            ISD::MemIndexedMode &AM,
259                                            SelectionDAG &DAG) const;
260 
261     /// SelectAddressRegReg - Given the specified addressed, check to see if it
262     /// can be represented as an indexed [r+r] operation.  Returns false if it
263     /// can be more efficiently represented with [r+imm].
264     bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
265                              SelectionDAG &DAG) const;
266 
267     /// SelectAddressRegImm - Returns true if the address N can be represented
268     /// by a base register plus a signed 16-bit displacement [r+imm], and if it
269     /// is not better represented as reg+reg.
270     bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
271                              SelectionDAG &DAG) const;
272 
273     /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
274     /// represented as an indexed [r+r] operation.
275     bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
276                                  SelectionDAG &DAG) const;
277 
278     /// SelectAddressRegImmShift - Returns true if the address N can be
279     /// represented by a base register plus a signed 14-bit displacement
280     /// [r+imm*4].  Suitable for use by STD and friends.
281     bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
282                                   SelectionDAG &DAG) const;
283 
284     Sched::Preference getSchedulingPreference(SDNode *N) const;
285 
286     /// LowerOperation - Provide custom lowering hooks for some operations.
287     ///
288     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
289 
290     /// ReplaceNodeResults - Replace the results of node with an illegal result
291     /// type with new values built out of custom code.
292     ///
293     virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
294                                     SelectionDAG &DAG) const;
295 
296     virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
297 
298     virtual void computeMaskedBitsForTargetNode(const SDValue Op,
299                                                 APInt &KnownZero,
300                                                 APInt &KnownOne,
301                                                 const SelectionDAG &DAG,
302                                                 unsigned Depth = 0) const;
303 
304     virtual MachineBasicBlock *
305       EmitInstrWithCustomInserter(MachineInstr *MI,
306                                   MachineBasicBlock *MBB) const;
307     MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
308                                         MachineBasicBlock *MBB, bool is64Bit,
309                                         unsigned BinOpcode) const;
310     MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
311                                                 MachineBasicBlock *MBB,
312                                             bool is8bit, unsigned Opcode) const;
313 
314     ConstraintType getConstraintType(const std::string &Constraint) const;
315 
316     /// Examine constraint string and operand type and determine a weight value.
317     /// The operand object must already have been set up with the operand type.
318     ConstraintWeight getSingleConstraintMatchWeight(
319       AsmOperandInfo &info, const char *constraint) const;
320 
321     std::pair<unsigned, const TargetRegisterClass*>
322       getRegForInlineAsmConstraint(const std::string &Constraint,
323                                    EVT VT) const;
324 
325     /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
326     /// function arguments in the caller parameter area.  This is the actual
327     /// alignment, not its logarithm.
328     unsigned getByValTypeAlignment(Type *Ty) const;
329 
330     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
331     /// vector.  If it is invalid, don't add anything to Ops.
332     virtual void LowerAsmOperandForConstraint(SDValue Op,
333                                               std::string &Constraint,
334                                               std::vector<SDValue> &Ops,
335                                               SelectionDAG &DAG) const;
336 
337     /// isLegalAddressingMode - Return true if the addressing mode represented
338     /// by AM is legal for this target, for a load/store of the specified type.
339     virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
340 
341     /// isLegalAddressImmediate - Return true if the integer value can be used
342     /// as the offset of the target addressing mode for load / store of the
343     /// given type.
344     virtual bool isLegalAddressImmediate(int64_t V, Type *Ty) const;
345 
346     /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
347     /// the offset of the target addressing mode.
348     virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
349 
350     virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
351 
352     /// getOptimalMemOpType - Returns the target specific optimal type for load
353     /// and store operations as a result of memset, memcpy, and memmove
354     /// lowering. If DstAlign is zero that means it's safe to destination
355     /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
356     /// means there isn't a need to check it against alignment requirement,
357     /// probably because the source does not need to be loaded. If
358     /// 'IsZeroVal' is true, that means it's safe to return a
359     /// non-scalar-integer type, e.g. empty string source, constant, or loaded
360     /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
361     /// constant so it does not need to be loaded.
362     /// It returns EVT::Other if the type should be determined using generic
363     /// target-independent logic.
364     virtual EVT
365     getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
366                         bool IsZeroVal, bool MemcpyStrSrc,
367                         MachineFunction &MF) const;
368 
369   private:
370     SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
371     SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
372 
373     bool
374     IsEligibleForTailCallOptimization(SDValue Callee,
375                                       CallingConv::ID CalleeCC,
376                                       bool isVarArg,
377                                       const SmallVectorImpl<ISD::InputArg> &Ins,
378                                       SelectionDAG& DAG) const;
379 
380     SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
381                                          int SPDiff,
382                                          SDValue Chain,
383                                          SDValue &LROpOut,
384                                          SDValue &FPOpOut,
385                                          bool isDarwinABI,
386                                          DebugLoc dl) const;
387 
388     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
389     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
390     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
391     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
392     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
393     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
394     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
395     SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
396     SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
397     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
398                          const PPCSubtarget &Subtarget) const;
399     SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
400                        const PPCSubtarget &Subtarget) const;
401     SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
402                                 const PPCSubtarget &Subtarget) const;
403     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
404                                       const PPCSubtarget &Subtarget) const;
405     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
406     SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl) const;
407     SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
408     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
409     SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
410     SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
411     SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
412     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
413     SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
414     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
415     SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
416     SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
417 
418     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
419                             CallingConv::ID CallConv, bool isVarArg,
420                             const SmallVectorImpl<ISD::InputArg> &Ins,
421                             DebugLoc dl, SelectionDAG &DAG,
422                             SmallVectorImpl<SDValue> &InVals) const;
423     SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall,
424                        bool isVarArg,
425                        SelectionDAG &DAG,
426                        SmallVector<std::pair<unsigned, SDValue>, 8>
427                          &RegsToPass,
428                        SDValue InFlag, SDValue Chain,
429                        SDValue &Callee,
430                        int SPDiff, unsigned NumBytes,
431                        const SmallVectorImpl<ISD::InputArg> &Ins,
432                        SmallVectorImpl<SDValue> &InVals) const;
433 
434     virtual SDValue
435       LowerFormalArguments(SDValue Chain,
436                            CallingConv::ID CallConv, bool isVarArg,
437                            const SmallVectorImpl<ISD::InputArg> &Ins,
438                            DebugLoc dl, SelectionDAG &DAG,
439                            SmallVectorImpl<SDValue> &InVals) const;
440 
441     virtual SDValue
442       LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
443                 bool isVarArg, bool doesNotRet, bool &isTailCall,
444                 const SmallVectorImpl<ISD::OutputArg> &Outs,
445                 const SmallVectorImpl<SDValue> &OutVals,
446                 const SmallVectorImpl<ISD::InputArg> &Ins,
447                 DebugLoc dl, SelectionDAG &DAG,
448                 SmallVectorImpl<SDValue> &InVals) const;
449 
450     virtual bool
451       CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
452                    bool isVarArg,
453                    const SmallVectorImpl<ISD::OutputArg> &Outs,
454                    LLVMContext &Context) const;
455 
456     virtual SDValue
457       LowerReturn(SDValue Chain,
458                   CallingConv::ID CallConv, bool isVarArg,
459                   const SmallVectorImpl<ISD::OutputArg> &Outs,
460                   const SmallVectorImpl<SDValue> &OutVals,
461                   DebugLoc dl, SelectionDAG &DAG) const;
462 
463     SDValue
464       LowerFormalArguments_Darwin(SDValue Chain,
465                                   CallingConv::ID CallConv, bool isVarArg,
466                                   const SmallVectorImpl<ISD::InputArg> &Ins,
467                                   DebugLoc dl, SelectionDAG &DAG,
468                                   SmallVectorImpl<SDValue> &InVals) const;
469     SDValue
470       LowerFormalArguments_SVR4(SDValue Chain,
471                                 CallingConv::ID CallConv, bool isVarArg,
472                                 const SmallVectorImpl<ISD::InputArg> &Ins,
473                                 DebugLoc dl, SelectionDAG &DAG,
474                                 SmallVectorImpl<SDValue> &InVals) const;
475 
476     SDValue
477       LowerCall_Darwin(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
478                        bool isVarArg, bool isTailCall,
479                        const SmallVectorImpl<ISD::OutputArg> &Outs,
480                        const SmallVectorImpl<SDValue> &OutVals,
481                        const SmallVectorImpl<ISD::InputArg> &Ins,
482                        DebugLoc dl, SelectionDAG &DAG,
483                        SmallVectorImpl<SDValue> &InVals) const;
484     SDValue
485     LowerCall_SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
486                    bool isVarArg, bool isTailCall,
487                    const SmallVectorImpl<ISD::OutputArg> &Outs,
488                    const SmallVectorImpl<SDValue> &OutVals,
489                    const SmallVectorImpl<ISD::InputArg> &Ins,
490                    DebugLoc dl, SelectionDAG &DAG,
491                    SmallVectorImpl<SDValue> &InVals) const;
492   };
493 }
494 
495 #endif   // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
496