• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1###########################################################
2## Commands for running tblgen to compile a td file
3##########################################################
4define transform-td-to-out
5$(if $(LOCAL_IS_HOST_MODULE),	\
6	$(call transform-host-td-to-out,$(1)),	\
7	$(call transform-device-td-to-out,$(1)))
8endef
9
10###########################################################
11## TableGen: Compile .td files to .inc.
12###########################################################
13
14# Set LOCAL_MODULE_CLASS to STATIC_LIBRARIES default (require
15# for macro local-intermediates-dir)
16ifeq ($(LOCAL_MODULE_CLASS),)
17	LOCAL_MODULE_CLASS := STATIC_LIBRARIES
18endif
19
20ifneq ($(strip $(TBLGEN_TABLES)),)
21
22intermediates := $(call local-intermediates-dir)
23tblgen_gen_tables := $(addprefix $(intermediates)/,$(TBLGEN_TABLES))
24LOCAL_GENERATED_SOURCES += $(tblgen_gen_tables)
25
26tblgen_source_dir := $(LOCAL_PATH)
27ifneq ($(TBLGEN_TD_DIR),)
28tblgen_source_dir := $(TBLGEN_TD_DIR)
29endif
30
31#
32# The directory and the .td directory is not the same.
33#
34ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/ARM/MCTargetDesc)
35$(intermediates)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
36$(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN)
37	$(call transform-td-to-out, register-info)
38
39$(intermediates)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
40$(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN)
41	$(call transform-td-to-out,instr-info)
42
43$(intermediates)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
44$(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN)
45	$(call transform-td-to-out,subtarget)
46endif
47
48ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/X86/MCTargetDesc)
49$(intermediates)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
50$(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN)
51	$(call transform-td-to-out, register-info)
52
53$(intermediates)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
54$(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN)
55	$(call transform-td-to-out,instr-info)
56
57$(intermediates)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
58$(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN)
59	$(call transform-td-to-out,subtarget)
60endif
61
62
63ifneq ($(filter %GenRegisterInfo.inc,$(tblgen_gen_tables)),)
64$(intermediates)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
65$(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
66	$(call transform-td-to-out,register-info)
67endif
68
69ifneq ($(filter %GenInstrInfo.inc,$(tblgen_gen_tables)),)
70$(intermediates)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
71$(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
72	$(call transform-td-to-out,instr-info)
73endif
74
75ifneq ($(filter %GenAsmWriter.inc,$(tblgen_gen_tables)),)
76$(intermediates)/%GenAsmWriter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
77$(intermediates)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
78	$(call transform-td-to-out,asm-writer)
79endif
80
81ifneq ($(filter %GenAsmWriter1.inc,$(tblgen_gen_tables)),)
82$(intermediates)/%GenAsmWriter1.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
83$(intermediates)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
84	$(call transform-td-to-out,asm-writer -asmwriternum=1)
85endif
86
87ifneq ($(filter %GenAsmMatcher.inc,$(tblgen_gen_tables)),)
88$(intermediates)/%GenAsmMatcher.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
89$(intermediates)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
90	$(call transform-td-to-out,asm-matcher)
91endif
92
93ifneq ($(filter %GenCodeEmitter.inc,$(tblgen_gen_tables)),)
94$(intermediates)/%GenCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
95$(intermediates)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
96	$(call transform-td-to-out,emitter)
97endif
98
99ifneq ($(filter %GenMCCodeEmitter.inc,$(tblgen_gen_tables)),)
100$(intermediates)/%GenMCCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
101$(intermediates)/%GenMCCodeEmitter.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
102	$(call transform-td-to-out,emitter -mc-emitter)
103endif
104
105ifneq ($(filter %GenMCPseudoLowering.inc,$(tblgen_gen_tables)),)
106$(intermediates)/%GenMCPseudoLowering.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
107$(intermediates)/%GenMCPseudoLowering.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
108	$(call transform-td-to-out,pseudo-lowering)
109endif
110
111ifneq ($(filter %GenDAGISel.inc,$(tblgen_gen_tables)),)
112$(intermediates)/%GenDAGISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
113$(intermediates)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
114	$(call transform-td-to-out,dag-isel)
115endif
116
117ifneq ($(filter %GenDisassemblerTables.inc,$(tblgen_gen_tables)),)
118$(intermediates)/%GenDisassemblerTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
119$(intermediates)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
120	$(call transform-td-to-out,disassembler)
121endif
122
123ifneq ($(filter %GenEDInfo.inc,$(tblgen_gen_tables)),)
124$(intermediates)/%GenEDInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
125$(intermediates)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
126	$(call transform-td-to-out,enhanced-disassembly-info)
127endif
128
129ifneq ($(filter %GenFastISel.inc,$(tblgen_gen_tables)),)
130$(intermediates)/%GenFastISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
131$(intermediates)/%GenFastISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
132	$(call transform-td-to-out,fast-isel)
133endif
134
135ifneq ($(filter %GenSubtargetInfo.inc,$(tblgen_gen_tables)),)
136$(intermediates)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
137$(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
138	$(call transform-td-to-out,subtarget)
139endif
140
141ifneq ($(filter %GenCallingConv.inc,$(tblgen_gen_tables)),)
142$(intermediates)/%GenCallingConv.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
143$(intermediates)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
144	$(call transform-td-to-out,callingconv)
145endif
146
147ifneq ($(filter %GenIntrinsics.inc,$(tblgen_gen_tables)),)
148$(intermediates)/%GenIntrinsics.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
149$(intermediates)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
150	$(call transform-td-to-out,tgt_intrinsics)
151endif
152
153ifneq ($(findstring ARMGenDecoderTables.inc,$(tblgen_gen_tables)),)
154$(intermediates)/ARMGenDecoderTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
155$(intermediates)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td $(TBLGEN)
156	$(call transform-td-to-out,arm-decoder)
157endif
158
159endif
160