1; RUN: llc < %s -disable-post-ra -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=SOFT 2; RUN: llc < %s -disable-post-ra -mtriple=armv7-gnueabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s -check-prefix=HARD 3 4; rdar://8984306 5define float @test1(float %x, float %y) nounwind { 6entry: 7; SOFT: test1: 8; SOFT: lsr r1, r1, #31 9; SOFT: bfi r0, r1, #31, #1 10 11; HARD: test1: 12; HARD: vmov.i32 [[REG1:(d[0-9]+)]], #0x80000000 13; HARD: vbsl [[REG1]], d 14 %0 = tail call float @copysignf(float %x, float %y) nounwind 15 ret float %0 16} 17 18define double @test2(double %x, double %y) nounwind { 19entry: 20; SOFT: test2: 21; SOFT: lsr r2, r3, #31 22; SOFT: bfi r1, r2, #31, #1 23 24; HARD: test2: 25; HARD: vmov.i32 [[REG2:(d[0-9]+)]], #0x80000000 26; HARD: vshl.i64 [[REG2]], [[REG2]], #32 27; HARD: vbsl [[REG2]], d1, d0 28 %0 = tail call double @copysign(double %x, double %y) nounwind 29 ret double %0 30} 31 32define double @test3(double %x, double %y, double %z) nounwind { 33entry: 34; SOFT: test3: 35; SOFT: vmov.i32 [[REG3:(d[0-9]+)]], #0x80000000 36; SOFT: vshl.i64 [[REG3]], [[REG3]], #32 37; SOFT: vbsl [[REG3]], 38 %0 = fmul double %x, %y 39 %1 = tail call double @copysign(double %0, double %z) nounwind 40 ret double %1 41} 42 43; rdar://9287902 44define float @test4() nounwind { 45entry: 46; SOFT: test4: 47; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1 48; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000 49; SOFT: vshr.u64 [[REG7]], [[REG7]], #32 50; SOFT: vbsl [[REG6]], [[REG7]], 51 %0 = tail call double (...)* @bar() nounwind 52 %1 = fptrunc double %0 to float 53 %2 = tail call float @copysignf(float 5.000000e-01, float %1) nounwind readnone 54 %3 = fadd float %1, %2 55 ret float %3 56} 57 58declare double @bar(...) 59declare double @copysign(double, double) nounwind 60declare float @copysignf(float, float) nounwind 61