1; RUN: llc < %s -march=arm -mattr=+neon,+v6t2 | FileCheck %s 2 3; Radar 7449043 4%struct.int32x4_t = type { <4 x i32> } 5 6define void @t() nounwind { 7entry: 8; CHECK: vmov.I64 q15, #0 9; CHECK: vmov.32 d30[0], 10; CHECK: vmov q8, q15 11 %tmp = alloca %struct.int32x4_t, align 16 12 call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* %tmp, i32 8192) nounwind 13 ret void 14} 15 16; Radar 7457110 17%struct.int32x2_t = type { <4 x i32> } 18 19define void @t2() nounwind { 20entry: 21; CHECK: vmov d30, d16 22; CHECK: vmov.32 r0, d30[0] 23 %asmtmp2 = tail call i32 asm sideeffect "vmov d30, $1\0Avmov.32 $0, d30[0]\0A", "=r,w,~{d30}"(<2 x i32> undef) nounwind 24 ret void 25} 26 27; Radar 9306086 28 29%0 = type { <8 x i8>, <16 x i8>* } 30 31define hidden void @conv4_8_E() nounwind { 32entry: 33%asmtmp31 = call %0 asm "vld1.u8 {$0}, [$1, :128]!\0A", "=w,=r,1"(<16 x i8>* undef) nounwind 34unreachable 35} 36 37; Radar 9037836 & 9119939 38 39define i32 @t3() nounwind { 40entry: 41tail call void asm sideeffect "flds s15, $0 \0A", "^Uv|m,~{s15}"(float 1.000000e+00) nounwind 42ret i32 0 43} 44 45; Radar 9037836 & 9119939 46 47@k.2126 = internal unnamed_addr global float 1.000000e+00 48define i32 @t4() nounwind { 49entry: 50call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}"(float* @k.2126) nounwind 51ret i32 0 52} 53 54; Radar 9037836 & 9119939 55 56define i32 @t5() nounwind { 57entry: 58call void asm sideeffect "flds s15, $0 \0A", "*^Uvm,~{s15}"(float* @k.2126) nounwind 59ret i32 0 60} 61 62; Radar 9307836 & 9119939 63 64define float @t6(float %y) nounwind { 65entry: 66; CHECK: t6 67; CHECK: flds s15, s0 68 %0 = tail call float asm "flds s15, $0", "=x"() nounwind 69 ret float %0 70} 71 72; Radar 9307836 & 9119939 73 74define double @t7(double %y) nounwind { 75entry: 76; CHECK: t7 77; CHECK: flds s15, d0 78 %0 = tail call double asm "flds s15, $0", "=x"() nounwind 79 ret double %0 80} 81 82; Radar 9307836 & 9119939 83 84define float @t8(float %y) nounwind { 85entry: 86; CHECK: t8 87; CHECK: flds s15, s0 88 %0 = tail call float asm "flds s15, $0", "=t"() nounwind 89 ret float %0 90} 91 92; Radar 9307836 & 9119939 93 94define i32 @t9(i32 %r0) nounwind { 95entry: 96; CHECK: t9 97; CHECK: movw r0, #27182 98 %0 = tail call i32 asm "movw $0, $1", "=r,j"(i32 27182) nounwind 99 ret i32 %0 100} 101 102; Radar 9866494 103 104define void @t10(i8* %f, i32 %g) nounwind { 105entry: 106; CHECK: t10 107; CHECK: str r1, [r0] 108 %f.addr = alloca i8*, align 4 109 store i8* %f, i8** %f.addr, align 4 110 call void asm "str $1, $0", "=*Q,r"(i8** %f.addr, i32 %g) nounwind 111 ret void 112} 113 114; Radar 10551006 115 116define <4 x i32> @t11(i32* %p) nounwind { 117entry: 118; CHECK: t11 119; CHECK: vld1.s32 {d16[], d17[]}, [r0] 120 %0 = tail call <4 x i32> asm "vld1.s32 {${0:e}[], ${0:f}[]}, [$1]", "=w,r"(i32* %p) nounwind 121 ret <4 x i32> %0 122} 123