1; RUN: llc -mtriple armv7 %s -o - | FileCheck %s 2 3; CHECK: f: 4define float @f(<4 x i16>* nocapture %in) { 5 ; CHECK: vldr 6 ; CHECK: vmovl.u16 7 %1 = load <4 x i16>* %in 8 ; CHECK: vcvt.f32.u32 9 %2 = uitofp <4 x i16> %1 to <4 x float> 10 %3 = extractelement <4 x float> %2, i32 0 11 %4 = extractelement <4 x float> %2, i32 1 12 %5 = extractelement <4 x float> %2, i32 2 13 14 ; CHECK: vadd.f32 15 %6 = fadd float %3, %4 16 %7 = fadd float %6, %5 17 18 ret float %7 19} 20 21; CHECK: g: 22define float @g(<4 x i8>* nocapture %in) { 23 ; CHECK: vldr 24 ; CHECK: vmovl.u8 25 ; CHECK: vmovl.u16 26 %1 = load <4 x i8>* %in 27 ; CHECK: vcvt.f32.u32 28 %2 = uitofp <4 x i8> %1 to <4 x float> 29 %3 = extractelement <4 x float> %2, i32 0 30 %4 = extractelement <4 x float> %2, i32 1 31 %5 = extractelement <4 x float> %2, i32 2 32 33 ; CHECK: vadd.f32 34 %6 = fadd float %3, %4 35 %7 = fadd float %6, %5 36 37 ret float %7 38} 39 40; CHECK: h: 41define <4 x i8> @h(<4 x float> %v) { 42 ; CHECK: vcvt.{{[us]}}32.f32 43 ; CHECK: vmovn.i32 44 %1 = fptoui <4 x float> %v to <4 x i8> 45 ret <4 x i8> %1 46} 47 48; CHECK: i: 49define <4 x i8> @i(<4 x i8>* %x) { 50 ; CHECK: vldr 51 ; CHECK: vmovl.s8 52 ; CHECK: vmovl.s16 53 ; CHECK: vrecpe 54 ; CHECK: vrecps 55 ; CHECK: vmul 56 ; CHECK: vmovn 57 %1 = load <4 x i8>* %x, align 4 58 %2 = sdiv <4 x i8> zeroinitializer, %1 59 ret <4 x i8> %2 60} 61