1; RUN: llc -mtriple=x86_64-apple-macosx < %s | FileCheck %s 2; rdar://7610418 3 4%ptr = type { i8* } 5%struct.s1 = type { %ptr, %ptr } 6%struct.s2 = type { i32, i8*, i8*, [256 x %struct.s1*], [8 x i32], i64, i8*, i32, i64, i64, i32, %struct.s3*, %struct.s3*, [49 x i64] } 7%struct.s3 = type { %struct.s3*, %struct.s3*, i32, i32, i32 } 8 9define fastcc i8* @t(i32 %base) nounwind { 10entry: 11; CHECK: t: 12; CHECK: leaq (%rax,%rax,4) 13 %0 = zext i32 %base to i64 14 %1 = getelementptr inbounds %struct.s2* null, i64 %0 15 br i1 undef, label %bb1, label %bb2 16 17bb1: 18; CHECK: %bb1 19; CHECK-NOT: shlq $9 20; CHECK-NOT: leaq 21; CHECK: call 22 %2 = getelementptr inbounds %struct.s2* null, i64 %0, i32 0 23 call void @bar(i32* %2) nounwind 24 unreachable 25 26bb2: 27; CHECK: %bb2 28; CHECK-NOT: leaq 29; CHECK: callq 30 %3 = call fastcc i8* @foo(%struct.s2* %1) nounwind 31 unreachable 32 33bb3: 34 ret i8* undef 35} 36 37declare void @bar(i32*) 38 39declare fastcc i8* @foo(%struct.s2*) nounwind 40 41; rdar://8773371 42 43declare void @printf(...) nounwind 44 45define void @commute(i32 %test_case, i32 %scale) nounwind ssp { 46; CHECK: commute: 47entry: 48 switch i32 %test_case, label %sw.bb307 [ 49 i32 1, label %sw.bb 50 i32 2, label %sw.bb 51 i32 3, label %sw.bb 52 ] 53 54sw.bb: ; preds = %entry, %entry, %entry 55 %mul = mul nsw i32 %test_case, 3 56 %mul20 = mul nsw i32 %mul, %scale 57 br i1 undef, label %if.end34, label %sw.bb307 58 59if.end34: ; preds = %sw.bb 60; CHECK: %if.end34 61; CHECK: imull 62; CHECK: leal 63; CHECK-NOT: imull 64 tail call void (...)* @printf(i32 %test_case, i32 %mul20) nounwind 65 %tmp = mul i32 %scale, %test_case 66 %tmp752 = mul i32 %tmp, 3 67 %tmp753 = zext i32 %tmp752 to i64 68 br label %bb.nph743.us 69 70for.body53.us: ; preds = %bb.nph743.us, %for.body53.us 71 %exitcond = icmp eq i64 undef, %tmp753 72 br i1 %exitcond, label %bb.nph743.us, label %for.body53.us 73 74bb.nph743.us: ; preds = %for.body53.us, %if.end34 75 br label %for.body53.us 76 77sw.bb307: ; preds = %sw.bb, %entry 78 ret void 79} 80 81; CSE physical register defining instruction across MBB boundary. 82; rdar://10660865 83define i32 @cross_mbb_phys_cse(i32 %a, i32 %b) nounwind ssp { 84entry: 85; CHECK: cross_mbb_phys_cse: 86; CHECK: cmpl 87; CHECK: ja 88 %cmp = icmp ugt i32 %a, %b 89 br i1 %cmp, label %return, label %if.end 90 91if.end: ; preds = %entry 92; CHECK-NOT: cmpl 93; CHECK: sbbl 94 %cmp1 = icmp ult i32 %a, %b 95 %. = sext i1 %cmp1 to i32 96 br label %return 97 98return: ; preds = %if.end, %entry 99 %retval.0 = phi i32 [ 1, %entry ], [ %., %if.end ] 100 ret i32 %retval.0 101} 102