455   if (Subtarget->hasNEON()) {  in ARMTargetLowering()
1030   if (Subtarget->hasNEON()) {  in getRegClassFor()
3240   bool UseNEON = !InGPR && Subtarget->hasNEON();  in LowerFCOPYSIGN()
3513   assert(ST->hasNEON() && "unexpected vector shift");  in LowerShift()
6330         Subtarget->hasNEON()) {  in EmitStructByval()
7166   if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()  in AddCombineToVPADDL()
7628   if (BVN && Subtarget->hasNEON() &&  in PerformORCombine()
7661   if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&  in PerformORCombine()
8457   if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||  in PerformVCVTCombine()
8494   if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||  in PerformVDIVCombine()
8749   assert(ST->hasNEON() && "unexpected vector shift");  in PerformShiftCombine()
8783   if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {  in PerformExtendCombine()
8825   if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||  in PerformSELECT_CCCombine()
9039     return Subtarget->hasNEON();  in allowsUnalignedMemoryAccesses()
9060       Subtarget->hasNEON()) {  in getOptimalMemOpType()