Searched refs:ANDI (Results 1 – 12 of 12) sorted by relevance
| /external/v8/src/mips/ |
| D | constants-mips.cc | 315 case ANDI: in InstructionType()
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| D | constants-mips.h | 267 ANDI = ((1 << 3) + 4) << kOpcodeShift, enumerator
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| D | disasm-mips.cc | 858 case ANDI: in DecodeTypeImmediate()
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| D | simulator-mips.cc | 2427 case ANDI: in DecodeTypeImmediate()
2551 case ANDI: in DecodeTypeImmediate()
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| D | assembler-mips.cc | 650 return GetOpcodeField(instr) == ANDI; in IsAndImmediate()
1248 GenInstrImmediate(ANDI, rs, rt, j); in andi()
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| /external/llvm/test/CodeGen/CellSPU/ |
| D | and_ops.ll | 186 ; ANDI instruction generation (i32 data type):
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| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| D | MBlazeDisassembler.cpp | 52 MBlaze::ORI, MBlaze::ANDI, MBlaze::XORI, MBlaze::ANDNI, //28,29,2A,2B
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| /external/qemu/tcg/ppc64/ |
| D | tcg-target.c | 309 #define ANDI OPCD( 28) macro
1316 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]); in tcg_out_op()
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| /external/qemu/tcg/ppc/ |
| D | tcg-target.c | 321 #define ANDI OPCD(28) macro
1432 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | c); in tcg_out_op()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 295 BuildMI(MBB, dl, TII->get(MBlaze::ANDI), IAMT) in EmitCustomShift()
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| D | MBlazeInstrInfo.td | 416 def ANDI : LogicI<0x29, "andi ", and>;
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUInstrInfo.td | 1354 // Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32
1360 // Hacked form of ANDI to zero-extend i16 quantities to i32. See the
1370 defm ANDI : AndWordImm;
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