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Searched refs:COPY_TO_REGCLASS (Results 1 – 15 of 15) sorted by relevance

/external/llvm/lib/Target/CellSPU/
DSPU64InstrInfo.td57 CodeFrag<(CGTIv4i32 (GBv4i32 (CEQv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
58 (COPY_TO_REGCLASS R64C:$rB, VECREG))), 0xb)>;
70 def r64: CodeFrag<(i32 (COPY_TO_REGCLASS CEQr64compare.Fragment, R32C))>;
71 def v2i64: CodeFrag<(i32 (COPY_TO_REGCLASS CEQv2i64compare.Fragment, R32C))>;
74 def r64mask: CodeFrag<(i32 (COPY_TO_REGCLASS
76 def v2i64mask: CodeFrag<(i32 (COPY_TO_REGCLASS
94 CodeFrag<(CLGTv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
95 (COPY_TO_REGCLASS R64C:$rB, VECREG))>;
98 CodeFrag<(CEQv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
99 (COPY_TO_REGCLASS R64C:$rB, VECREG))>;
[all …]
DSPUISelDAGToDAG.cpp755 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT, in Select()
839 Result = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VT, in Select()
912 VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT, in SelectSHLi64()
957 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSHLi64()
979 VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT, in SelectSRLi64()
1026 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSRLi64()
1048 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSRAi64()
1056 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSRAi64()
1104 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSRAi64()
1132 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT, in SelectI64Constant()
[all …]
DSPUInstrInfo.td1428 (COPY_TO_REGCLASS R8C:$rA, VECREG)>;
1431 (COPY_TO_REGCLASS R16C:$rA, VECREG)>;
1434 (COPY_TO_REGCLASS R32C:$rA, VECREG)>;
1437 (COPY_TO_REGCLASS R64C:$rA, VECREG)>;
1440 (COPY_TO_REGCLASS R32FP:$rA, VECREG)>;
1443 (COPY_TO_REGCLASS R64FP:$rA, VECREG)>;
1446 (COPY_TO_REGCLASS (v16i8 VECREG:$rA), R8C)>;
1449 (COPY_TO_REGCLASS (v8i16 VECREG:$rA), R16C)>;
1452 (COPY_TO_REGCLASS (v4i32 VECREG:$rA), R32C)>;
1455 (COPY_TO_REGCLASS (v2i64 VECREG:$rA), R64C)>;
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DSPUISelLowering.cpp2761 SDValue extended = SDValue(DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, in LowerSIGN_EXTEND()
/external/llvm/include/llvm/Target/
DTargetOpcodes.h66 COPY_TO_REGCLASS = 10, enumerator
DTarget.td724 def COPY_TO_REGCLASS : Instruction {
/external/llvm/lib/Target/X86/
DX86InstrCompiler.td1294 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1301 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1329 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1336 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1368 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1372 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1390 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1394 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1400 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1405 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
[all …]
DX86InstrSSE.td248 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
250 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
288 (COPY_TO_REGCLASS FR32:$src, VR128)>;
290 (COPY_TO_REGCLASS FR32:$src, VR128)>;
293 (COPY_TO_REGCLASS FR64:$src, VR128)>;
295 (COPY_TO_REGCLASS FR64:$src, VR128)>;
556 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
558 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
577 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
579 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
[all …]
DX86InstrFPStack.td665 def : Pat<(f64 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>,
667 def : Pat<(f80 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>,
669 def : Pat<(f80 (fextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>,
675 def : Pat<(f32 (fround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>,
677 def : Pat<(f32 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>,
679 def : Pat<(f64 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>,
DX86ISelDAGToDAG.cpp2485 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, in Select()
2515 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, in Select()
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td5011 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
5014 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
5067 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
5070 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
5512 (v2f32 (COPY_TO_REGCLASS (Inst
5514 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5520 (v2f32 (COPY_TO_REGCLASS (Inst
5522 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5525 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5531 (v2f32 (COPY_TO_REGCLASS (Inst
[all …]
DARMInstrVFP.td454 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
457 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp707 if (Opc == TargetOpcode::COPY_TO_REGCLASS) { in EmitMachineNode()
DScheduleDAGRRList.cpp2914 TargetOpcode::COPY_TO_REGCLASS) in AddPseudoTwoAddrDeps()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.td1560 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1562 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1565 (COPY_TO_REGCLASS F4RC:$src, F8RC)>;