| /external/llvm/lib/VMCore/ |
| D | Dominators.cpp | 99 bool DominatorTree::dominates(const Instruction *Def, in dominates() argument
102 const BasicBlock *DefBB = Def->getParent(); in dominates()
113 if (Def == User) in dominates()
120 if (isa<InvokeInst>(Def) || isa<PHINode>(User)) in dominates()
121 return dominates(Def, UseBB); in dominates()
128 for (; &*I != Def && &*I != User; ++I) in dominates()
131 return &*I == Def; in dominates()
136 bool DominatorTree::dominates(const Instruction *Def, in dominates() argument
138 const BasicBlock *DefBB = Def->getParent(); in dominates()
151 const InvokeInst *II = dyn_cast<InvokeInst>(Def); in dominates()
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| /external/llvm/lib/CodeGen/ |
| D | MachineCopyPropagation.cpp | 110 static bool isNopCopy(MachineInstr *CopyMI, unsigned Def, unsigned Src, in isNopCopy() argument
113 if (Def == SrcSrc) in isNopCopy()
115 if (TRI->isSubRegister(SrcSrc, Def)) { in isNopCopy()
117 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); in isNopCopy()
138 unsigned Def = MI->getOperand(0).getReg(); in CopyPropagateBlock() local
141 if (TargetRegisterInfo::isVirtualRegister(Def) || in CopyPropagateBlock()
149 if (!ReservedRegs.test(Def) && in CopyPropagateBlock()
151 isNopCopy(CopyMI, Def, Src, TRI)) { in CopyPropagateBlock()
169 I->clearRegisterKills(Def, TRI); in CopyPropagateBlock()
195 SourceNoLongerAvailable(Def, SrcMap, AvailCopyMap); in CopyPropagateBlock()
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| D | LiveVariables.cpp | 199 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef() local
200 if (!Def) in FindLastPartialDef()
202 unsigned Dist = DistanceMap[Def]; in FindLastPartialDef()
205 LastDef = Def; in FindLastPartialDef()
292 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastRefOrPartRef() local
293 if (Def && Def != LastDef) { in FindLastRefOrPartRef()
296 unsigned Dist = DistanceMap[Def]; in FindLastRefOrPartRef()
341 MachineInstr *Def = PhysRegDef[SubReg]; in HandlePhysRegKill() local
342 if (Def && Def != LastDef) { in HandlePhysRegKill()
345 unsigned Dist = DistanceMap[Def]; in HandlePhysRegKill()
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| D | LiveInterval.cpp | 52 VNInfo *LiveInterval::createDeadDef(SlotIndex Def, in createDeadDef() argument
54 assert(!Def.isDead() && "Cannot define a value at the dead slot"); in createDeadDef()
55 iterator I = find(Def); in createDeadDef()
57 VNInfo *VNI = getNextValue(Def, VNInfoAllocator); in createDeadDef()
58 ranges.push_back(LiveRange(Def, Def.getDeadSlot(), VNI)); in createDeadDef()
61 if (SlotIndex::isSameInstr(Def, I->start)) { in createDeadDef()
62 assert(I->start == Def && "Cannot insert def, already live"); in createDeadDef()
63 assert(I->valno->def == Def && "Inconsistent existing value def"); in createDeadDef()
66 assert(SlotIndex::isEarlierInstr(Def, I->start) && "Already live at def"); in createDeadDef()
67 VNInfo *VNI = getNextValue(Def, VNInfoAllocator); in createDeadDef()
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| D | ExecutionDepsFix.cpp | 119 int Def; member
351 LiveRegs[rx].Def = -(1 << 20); in enterBasicBlock()
364 LiveRegs[rx].Def = -1; in enterBasicBlock()
382 LiveRegs[rx].Def = std::max(LiveRegs[rx].Def, fi->second[rx].Def); in enterBasicBlock()
422 LiveRegs[i].Def -= CurInstr; in leaveBasicBlock()
475 unsigned Clearance = CurInstr - LiveRegs[rx].Def; in processDefs()
476 LiveRegs[rx].Def = CurInstr; in processDefs()
588 if (LR.Def < i->Def) { in visitSoftInstr()
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| D | SplitKit.cpp | 395 SlotIndex Def = OldVNI->def; in defValue() local
396 LI->addRange(LiveRange(Def, Def.getDeadSlot(), OldVNI)); in defValue()
402 SlotIndex Def = VNI->def; in defValue() local
403 LI->addRange(LiveRange(Def, Def.getDeadSlot(), VNI)); in defValue()
422 SlotIndex Def = VNI->def; in forceRecompute() local
423 Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getDeadSlot(), VNI)); in forceRecompute()
434 SlotIndex Def; in defFromParent() local
444 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, TRI, Late); in defFromParent()
450 Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late) in defFromParent()
456 return defValue(RegIdx, ParentVNI, Def); in defFromParent()
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| D | MachineLICM.cpp | 154 unsigned Def; member
157 : MI(mi), Def(def), FI(fi) {} in CandidateInfo()
167 void HoistPostRA(MachineInstr *MI, unsigned Def);
410 unsigned Def = 0; in ProcessMI() local
460 if (Def) in ProcessMI()
463 Def = Reg; in ProcessMI()
481 if (Def && !RuledOut) { in ProcessMI()
485 Candidates.push_back(CandidateInfo(MI, Def, FI)); in ProcessMI()
561 unsigned Def = Candidates[i].Def; in HoistRegionPostRA() local
562 if (!PhysRegClobbers.test(Def) && !TermRegs.test(Def)) { in HoistRegionPostRA()
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| D | PeepholeOptimizer.cpp | 312 unsigned Def = 0; in optimizeBitcastInstr() local
322 Def = Reg; in optimizeBitcastInstr()
330 assert(Def && Src && "Malformed bitcast instruction!"); in optimizeBitcastInstr()
357 if (MRI->getRegClass(SrcSrc) != MRI->getRegClass(Def)) in optimizeBitcastInstr()
360 MRI->replaceRegWith(Def, SrcSrc); in optimizeBitcastInstr()
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| /external/llvm/utils/TableGen/ |
| D | DAGISelMatcherGen.cpp | 583 Record *Def = DI->getDef(); in EmitResultLeafAsOperand() local
584 if (Def->isSubClassOf("Register")) { in EmitResultLeafAsOperand()
586 CGP.getTargetInfo().getRegBank().getReg(Def); in EmitResultLeafAsOperand()
592 if (Def->getName() == "zero_reg") { in EmitResultLeafAsOperand()
600 if (Def->isSubClassOf("RegisterOperand")) in EmitResultLeafAsOperand()
601 Def = Def->getValueAsDef("RegClass"); in EmitResultLeafAsOperand()
602 if (Def->isSubClassOf("RegisterClass")) { in EmitResultLeafAsOperand()
603 std::string Value = getQualifiedName(Def) + "RegClassID"; in EmitResultLeafAsOperand()
610 if (Def->isSubClassOf("SubRegIndex")) { in EmitResultLeafAsOperand()
611 std::string Value = getQualifiedName(Def); in EmitResultLeafAsOperand()
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| D | SetTheory.cpp | 227 void expand(SetTheory &ST, Record *Def, RecSet &Elts) { in expand()
228 ST.evaluate(Def->getValueInit(FieldName), Elts); in expand()
264 if (DefInit *Def = dynamic_cast<DefInit*>(Expr)) { in evaluate() local
265 if (const RecVec *Result = expand(Def->getDef())) in evaluate()
267 Elts.insert(Def->getDef()); in evaluate()
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| D | CodeGenRegisters.cpp | 583 void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) { in expand()
584 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices"); in expand()
586 ListInit *SubRegs = Def->getValueAsListInit("SubRegs"); in expand()
588 throw TGError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch"); in expand()
590 throw TGError(Def->getLoc(), "Tuples must have at least 2 sub-registers"); in expand()
604 Record *RegisterCl = Def->getRecords().getClass("Register"); in expand()
626 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords()); in expand()
662 NewReg->addValue(*Def->getValue(Field)); in expand()
1037 CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) { in getSubRegIdx() argument
1038 CodeGenSubRegIndex *&Idx = Def2SubRegIdx[Def]; in getSubRegIdx()
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| D | FixedLenDecoderEmitter.cpp | 1698 const Record &Def = *CGI.TheDef; in populateInstruction() local
1706 if (Def.getValueAsBit("isAsmParserOnly") || in populateInstruction()
1707 Def.getValueAsBit("isCodeGenOnly")) in populateInstruction()
1710 BitsInit &Bits = getBitsField(Def, "Inst"); in populateInstruction()
1717 std::string InstDecoder = Def.getValueAsString("DecoderMethod"); in populateInstruction()
1732 DagInit *Out = Def.getValueAsDag("OutOperandList"); in populateInstruction()
1733 DagInit *In = Def.getValueAsDag("InOperandList"); in populateInstruction()
2018 const Record *Def = Inst->TheDef; in run() local
2019 unsigned Size = Def->getValueAsInt("Size"); in run()
2020 if (Def->getValueAsString("Namespace") == "TargetOpcode" || in run()
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| /external/valgrind/main/memcheck/tests/ |
| D | origin1-yes.stderr.exp | 57 Def 1 of 3
59 Def 2 of 3
61 Def 3 of 3
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| /external/llvm/lib/Transforms/Utils/ |
| D | SimplifyIndVar.cpp | 269 Instruction *Def, in pushIVUsers() argument
273 for (Value::use_iterator UI = Def->use_begin(), E = Def->use_end(); in pushIVUsers()
281 if (User != Def && Simplified.insert(User)) in pushIVUsers()
282 SimpleIVUsers.push_back(std::make_pair(User, Def)); in pushIVUsers()
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| /external/llvm/include/llvm/Analysis/ |
| D | MemoryDependenceAnalysis.h | 74 Def, enumerator
107 return MemDepResult(PairTy(Inst, Def)); in getDef()
132 bool isDef() const { return Value.getInt() == Def; } in isDef()
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| /external/llvm/examples/OCaml-Kaleidoscope/Chapter3/ |
| D | token.ml | 9 | Def | Extern Constructor
|
| /external/llvm/examples/OCaml-Kaleidoscope/Chapter4/ |
| D | token.ml | 9 | Def | Extern Constructor
|
| /external/llvm/examples/OCaml-Kaleidoscope/Chapter2/ |
| D | token.ml | 9 | Def | Extern Constructor
|
| /external/antlr/antlr-3.4/tool/src/main/resources/org/antlr/codegen/templates/Delphi/ |
| D | Delphi.stg | 1672 (IfThen(Assigned(<scope>),Def(<scope>).<attr.name>,<initValue(attr.type)>))
1703 tokenLabelPropertyRef_text(scope,attr) ::= "(Def(<scope>).Text)"
1704 tokenLabelPropertyRef_type(scope,attr) ::= "(Def(<scope>).TokenType)"
1705 tokenLabelPropertyRef_line(scope,attr) ::= "(Def(<scope>).Line)"
1706 tokenLabelPropertyRef_pos(scope,attr) ::= "(Def(<scope>).CharPositionInLine)"
1707 tokenLabelPropertyRef_channel(scope,attr) ::= "(Def(<scope>).Channel)"
1708 tokenLabelPropertyRef_index(scope,attr) ::= "(Def(<scope>).TokenIndex)"
1710 tokenLabelPropertyRef_int(scope,attr) ::= "(StrToIntDef(Def(<scope>).Text,0))"
1712 ruleLabelPropertyRef_start(scope,attr) ::= "(IfThen(Assigned(<scope>), Def(<scope>).Start, nil) as …
1713 ruleLabelPropertyRef_stop(scope,attr) ::= "(Def(<scope>).Stop as I<labelType>)"
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| /external/protobuf/gtest/test/ |
| D | gtest_list_tests_unittest_.cc | 58 TEST(Abc, Def) { in TEST() argument
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| /external/chromium/testing/gtest/test/ |
| D | gtest_list_tests_unittest_.cc | 58 TEST(Abc, Def) { in TEST() argument
|
| /external/gtest/test/ |
| D | gtest_list_tests_unittest_.cc | 58 TEST(Abc, Def) { in TEST() argument
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| /external/llvm/examples/OCaml-Kaleidoscope/Chapter5/ |
| D | token.ml | 9 | Def | Extern Constructor
|
| /external/llvm/examples/OCaml-Kaleidoscope/Chapter6/ |
| D | token.ml | 9 | Def | Extern Constructor
|
| /external/llvm/examples/OCaml-Kaleidoscope/Chapter7/ |
| D | token.ml | 9 | Def | Extern Constructor
|