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Searched refs:ImplicitDefs (Results 1 – 12 of 12) sorted by relevance

/external/llvm/include/llvm/MC/
DMCInstrDesc.h144 const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr variable
482 return ImplicitDefs; in getImplicitDefs()
488 if (ImplicitDefs == 0) return 0; in getNumImplicitDefs()
490 for (; ImplicitDefs[i]; ++i) /*empty*/; in getNumImplicitDefs()
506 if (const uint16_t *ImpDefs = ImplicitDefs) in hasImplicitDefOfPhysReg()
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1186 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_r()
1208 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rr()
1232 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rrr()
1253 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_ri()
1276 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rii()
1297 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rf()
1321 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rri()
1345 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rrii()
1361 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_i()
1378 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_ii()
DScheduleDAGFast.cpp426 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
504 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
DScheduleDAGSDNodes.cpp125 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) { in CheckForPhysRegDependency()
DScheduleDAGRRList.cpp1170 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
1296 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
/external/llvm/utils/TableGen/
DCodeGenInstruction.cpp327 ImplicitDefs = R->getValueAsListOfDefs("Defs"); in CodeGenInstruction()
345 if (ImplicitDefs.empty()) return MVT::Other; in HasOneImplicitDefWithKnownVT()
348 Record *FirstImplicitDef = ImplicitDefs[0]; in HasOneImplicitDefWithKnownVT()
DCodeGenInstruction.h216 std::vector<Record*> ImplicitDefs, ImplicitUses; variable
DDAGISelMatcherGen.cpp788 HandledReg = II.ImplicitDefs[0]; in EmitResultInstructionAsOperand()
913 HandledReg = II.ImplicitDefs[0]; in EmitResultCode()
DCodeGenDAGPatterns.cpp1551 if (!InstInfo.ImplicitDefs.empty()) { in ApplyTypeConstraints()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp313 .addReg(II.ImplicitDefs[0])); in FastEmitInst_r()
335 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rr()
360 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rrr()
382 .addReg(II.ImplicitDefs[0])); in FastEmitInst_ri()
404 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rf()
429 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rri()
448 .addReg(II.ImplicitDefs[0])); in FastEmitInst_i()
468 .addReg(II.ImplicitDefs[0])); in FastEmitInst_ii()
/external/llvm/lib/CodeGen/
DMachineInstr.cpp530 if (MCID->ImplicitDefs) in addImplicitDefUseOperands()
/external/llvm/docs/
DCodeGenerator.rst1258 ``TargetInstrInfo::get(opcode)::ImplicitDefs``, where ``opcode`` is the opcode