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Searched refs:MCInstrDesc (Results 1 – 25 of 68) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h25 class MCInstrDesc; variable
197 const MCInstrDesc &MCID) { in BuildMI()
206 const MCInstrDesc &MCID, in BuildMI()
219 const MCInstrDesc &MCID, in BuildMI()
229 const MCInstrDesc &MCID, in BuildMI()
239 const MCInstrDesc &MCID, in BuildMI()
257 const MCInstrDesc &MCID) { in BuildMI()
266 const MCInstrDesc &MCID) { in BuildMI()
275 const MCInstrDesc &MCID) { in BuildMI()
291 const MCInstrDesc &MCID) { in BuildMI()
[all …]
DDFAPacketizer.h35 class MCInstrDesc; variable
68 bool canReserveResources(const llvm::MCInstrDesc *MID);
72 void reserveResources(const llvm::MCInstrDesc *MID);
DMachineInstr.h65 const MCInstrDesc *MCID; // Instruction descriptor.
108 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
113 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
118 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
125 const MCInstrDesc &MCID);
254 const MCInstrDesc &getDesc() const { return *MCID; }
937 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
DScheduleDAG.h38 class MCInstrDesc; variable
543 const MCInstrDesc *getInstrDesc(const SUnit *SU) const {
585 const MCInstrDesc *getNodeDesc(const SDNode *Node) const;
/external/llvm/include/llvm/MC/
DMCInstrInfo.h27 const MCInstrDesc *Desc; // Raw array to allow static init'n
35 void InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND, in InitMCInstrInfo()
48 const MCInstrDesc &get(unsigned Opcode) const { in get()
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.h25 class MCInstrDesc; variable
52 const MCInstrDesc &II,
66 const MCInstrDesc *II,
76 const MCInstrDesc *II,
DInstrEmitter.cpp132 const MCInstrDesc &II = TII->get(User->getMachineOpcode()); in EmitCopyFromReg()
207 const MCInstrDesc &II, in CreateVirtualRegisters()
295 const MCInstrDesc *II, in AddRegisterOperand()
305 const MCInstrDesc &MCID = MI->getDesc(); in AddRegisterOperand()
360 const MCInstrDesc *II, in AddOperand()
605 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); in EmitRegSequence()
651 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); in EmitDbgValue()
722 const MCInstrDesc &II = TII->get(Opc); in EmitMachineNode()
807 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); in EmitMachineNode()
DFastISel.cpp636 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); in SelectCall()
1167 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_()
1177 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_r()
1197 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_rr()
1219 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_rrr()
1242 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_ri()
1263 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_rii()
1286 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_rf()
1308 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_rri()
1332 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_rrii()
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DScheduleDAGFast.cpp252 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors()
425 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT()
503 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp()
/external/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
43 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
46 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
DARMBaseInstrInfo.h242 const MCInstrDesc &DefMCID,
246 const MCInstrDesc &DefMCID,
250 const MCInstrDesc &UseMCID,
254 const MCInstrDesc &UseMCID,
258 const MCInstrDesc &DefMCID,
260 const MCInstrDesc &UseMCID,
DARMCodeEmitter.cpp101 const MCInstrDesc &MCID,
107 const MCInstrDesc &MCID) const;
279 const MCInstrDesc &MCID = MI.getDesc(); in getHiLo16ImmOpValue()
481 const MCInstrDesc &MCID = MI.getDesc(); in getMachineOpValue()
817 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelInstruction()
844 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelJTInstruction()
1011 const MCInstrDesc &MCID, in getMachineSoRegOpValue()
1081 const MCInstrDesc &MCID) const { in getAddrModeSBit()
1093 const MCInstrDesc &MCID = MI.getDesc(); in emitDataProcessingInstruction()
1196 const MCInstrDesc &MCID = MI.getDesc(); in emitLoadStoreInstruction()
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DMLxExpansionPass.cpp140 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
221 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
222 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
278 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions()
DThumb2SizeReduction.cpp192 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { in HasImplicitCPSRDef()
512 const MCInstrDesc &MCID = MI->getDesc(); in ReduceSpecial()
642 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2); in ReduceTo2Addr()
656 const MCInstrDesc &MCID = MI->getDesc(); in ReduceTo2Addr()
715 const MCInstrDesc &MCID = MI->getDesc(); in ReduceToNarrow()
734 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1); in ReduceToNarrow()
DARMBaseInstrInfo.cpp147 const MCInstrDesc &MCID = MI->getDesc(); in convertToThreeAddress()
551 const MCInstrDesc &MCID = MI->getDesc(); in GetInstSizeInBytes()
1660 const MCInstrDesc &DefDesc = DefMI->getDesc(); in optimizeSelect()
1767 const MCInstrDesc &Desc = MI.getDesc(); in rewriteARMFrameIndex()
2243 const MCInstrDesc &DefMCID = DefMI->getDesc(); in FoldImmediate()
2253 const MCInstrDesc &UseMCID = UseMI->getDesc(); in FoldImmediate()
2351 const MCInstrDesc &Desc = MI->getDesc(); in getNumMicroOps()
2452 const MCInstrDesc &DefMCID, in getVLDMDefCycle()
2493 const MCInstrDesc &DefMCID, in getLDMDefCycle()
2528 const MCInstrDesc &UseMCID, in getVSTMUseCycle()
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DThumb1RegisterInfo.cpp241 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); in emitThumbRegPlusImmediate()
291 const MCInstrDesc &MCID = TII.get(ExtraOpc); in emitThumbRegPlusImmediate()
360 const MCInstrDesc &MCID = TII.get(ARM::tRSB); in emitThumbConstant()
394 const MCInstrDesc &Desc = MI.getDesc(); in rewriteFrameIndex()
/external/llvm/lib/CodeGen/
DDFAPacketizer.cpp66 bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) { in canReserveResources()
78 void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) { in reserveResources()
92 const llvm::MCInstrDesc &MID = MI->getDesc(); in canReserveResources()
99 const llvm::MCInstrDesc &MID = MI->getDesc(); in reserveResources()
DScoreboardHazardRecognizer.cpp128 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType()
184 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
DTargetInstrInfoImpl.cpp63 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstruction()
128 const MCInstrDesc &MCID = MI->getDesc(); in findCommutedOpIndices()
163 const MCInstrDesc &MCID = MI->getDesc(); in PredicateInstruction()
DPeepholeOptimizer.cpp415 const MCInstrDesc &MCID = MI->getDesc(); in isLoadFoldable()
435 const MCInstrDesc &MCID = MI->getDesc(); in isMoveImmediate()
/external/llvm/lib/Target/PowerPC/
DPPCHazardRecognizers.cpp27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
94 const MCInstrDesc &MCID = TII.get(Opcode); in GetInstrType()
/external/llvm/lib/Target/X86/
DX86CodeEmitter.cpp72 const MCInstrDesc *Desc) const;
76 const MCInstrDesc *Desc) const;
82 void emitInstruction(MachineInstr &MI, const MCInstrDesc *Desc);
143 const MCInstrDesc &Desc = I->getDesc(); in runOnMachineFunction()
161 const MCInstrDesc &Desc = MI.getDesc(); in determineREX()
602 static const MCInstrDesc *UpdateOp(MachineInstr &MI, const X86InstrInfo *II, in UpdateOp()
604 const MCInstrDesc *Desc = &II->get(Opcode); in UpdateOp()
657 const MCInstrDesc *Desc) const { in emitOpcodePrefix()
806 const MCInstrDesc *Desc) const { in emitVEXOpcodePrefix()
1095 const MCInstrDesc *Desc) { in emitInstruction()
DX86InstrBuilder.h152 const MCInstrDesc &MCID = MI->getDesc();
/external/llvm/lib/Target/
DTargetInstrInfo.cpp34 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp126 const MCInst &MI, const MCInstrDesc &Desc,
134 const MCInst &MI, const MCInstrDesc &Desc,
444 const MCInstrDesc &Desc, in EmitVEXOpcodePrefix()
728 const MCInstrDesc &Desc) { in DetermineREXPrefix()
855 const MCInstrDesc &Desc, in EmitOpcodePrefix()
969 const MCInstrDesc &Desc = MCII.get(Opcode); in EncodeInstruction()

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