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Searched refs:NewOpc (Results 1 – 16 of 16) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp776 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local
777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) in MergeBaseUpdateLSMultiple()
875 unsigned NewOpc = 0; in MergeBaseUpdateLoadStore() local
893 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, AddSub); in MergeBaseUpdateLoadStore()
912 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, AddSub); in MergeBaseUpdateLoadStore()
930 BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) in MergeBaseUpdateLoadStore()
939 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore()
941 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
946 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
953 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
[all …]
DThumb2InstrInfo.cpp439 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in rewriteT2FrameIndex() local
440 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
473 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local
483 NewOpc = immediateOffsetOpcode(Opcode); in rewriteT2FrameIndex()
495 NewOpc = negativeOffsetOpcode(Opcode); in rewriteT2FrameIndex()
500 NewOpc = positiveOffsetOpcode(Opcode); in rewriteT2FrameIndex()
521 if (NewOpc != Opcode) in rewriteT2FrameIndex()
522 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
555 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
DARMConstantIslandPass.cpp1700 unsigned NewOpc = 0; in optimizeThumb2Instructions() local
1707 NewOpc = ARM::tLEApcrel; in optimizeThumb2Instructions()
1714 NewOpc = ARM::tLDRpci; in optimizeThumb2Instructions()
1721 if (!NewOpc) in optimizeThumb2Instructions()
1734 U.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Instructions()
1754 unsigned NewOpc = 0; in optimizeThumb2Branches() local
1760 NewOpc = ARM::tB; in optimizeThumb2Branches()
1765 NewOpc = ARM::tBcc; in optimizeThumb2Branches()
1771 if (NewOpc) { in optimizeThumb2Branches()
1776 Br.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Branches()
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DARMISelLowering.cpp2376 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) in LowerINTRINSIC_WO_CHAIN() local
2378 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
4903 unsigned NewOpc = 0; in LowerMUL() local
4908 NewOpc = ARMISD::VMULLs; in LowerMUL()
4913 NewOpc = ARMISD::VMULLu; in LowerMUL()
4918 NewOpc = ARMISD::VMULLs; in LowerMUL()
4921 NewOpc = ARMISD::VMULLu; in LowerMUL()
4925 NewOpc = ARMISD::VMULLu; in LowerMUL()
4930 if (!NewOpc) { in LowerMUL()
4949 return DAG.getNode(NewOpc, DL, VT, Op0, Op1); in LowerMUL()
[all …]
DThumb1RegisterInfo.cpp505 unsigned NewOpc = convertToNonSPOpcode(Opcode); in rewriteFrameIndex() local
506 if (NewOpc != Opcode && FrameReg != ARM::SP) in rewriteFrameIndex()
507 MI.setDesc(TII.get(NewOpc)); in rewriteFrameIndex()
DARMExpandPseudoInsts.cpp944 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI() local
946 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMI()
975 unsigned NewOpc = ARM::VSTMDIA; in ExpandMI() local
977 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMI()
1006 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q : in ExpandMI() local
1009 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMI()
DARMISelDAGToDAG.cpp3008 unsigned NewOpc = ARM::LDREXD; in Select() local
3010 NewOpc = ARM::t2LDREXD; in Select()
3024 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(), in Select()
3094 unsigned NewOpc = ARM::STREXD; in Select() local
3096 NewOpc = ARM::t2STREXD; in Select()
3098 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(), in Select()
/external/llvm/lib/Target/CellSPU/
DSPUISelDAGToDAG.cpp608 unsigned NewOpc = 0; in Select() local
622 NewOpc = SPU::AIr32; in Select()
627 NewOpc = SPU::Ar32; in Select()
860 NewOpc = SPU::Ar32; in Select()
866 NewOpc = SPU::AIr32; in Select()
882 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops); in Select()
884 return CurDAG->getMachineNode(NewOpc, dl, OpVT, Ops, n_ops); in Select()
DSPUISelLowering.cpp743 unsigned NewOpc = ISD::ANY_EXTEND; in LowerLOAD() local
746 NewOpc = ISD::FP_EXTEND; in LowerLOAD()
748 result = DAG.getNode(NewOpc, dl, OutVT, result); in LowerLOAD()
/external/llvm/lib/Target/X86/
DX86MCInstLower.cpp223 static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) { in LowerSubReg32_Op0() argument
224 OutMI.setOpcode(NewOpc); in LowerSubReg32_Op0()
228 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) { in LowerUnaryToTwoAddr() argument
229 OutMI.setOpcode(NewOpc); in LowerUnaryToTwoAddr()
DX86InstrInfo.cpp3333 unsigned NewOpc; in optimizeCompareInstr() local
3335 NewOpc = GetCondBranchFromCond(NewCC); in optimizeCompareInstr()
3337 NewOpc = getSETFromCond(NewCC, HasMemoryOperand); in optimizeCompareInstr()
3340 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(), in optimizeCompareInstr()
3347 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc)); in optimizeCompareInstr()
3807 unsigned NewOpc = 0; in foldMemoryOperandImpl() local
3811 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; in foldMemoryOperandImpl()
3812 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; in foldMemoryOperandImpl()
3813 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; in foldMemoryOperandImpl()
3814 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; in foldMemoryOperandImpl()
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/external/llvm/lib/Target/Mips/
DMipsLongBranch.cpp220 unsigned NewOpc = TII->GetOppositeBranchOpc(Br->getOpcode()); in replaceBranch() local
221 const MCInstrDesc &NewDesc = TII->get(NewOpc); in replaceBranch()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp6759 unsigned NewOpc; in processInstruction() local
6762 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; in processInstruction()
6763 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; in processInstruction()
6764 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; in processInstruction()
6768 TmpInst.setOpcode(NewOpc); in processInstruction()
7233 unsigned NewOpc; in processInstruction() local
7236 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; in processInstruction()
7237 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; in processInstruction()
7238 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; in processInstruction()
7239 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; in processInstruction()
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/external/llvm/lib/CodeGen/
DMachineLICM.cpp1255 unsigned NewOpc = in ExtractHoistableLoad() local
1260 if (NewOpc == 0) return 0; in ExtractHoistableLoad()
1261 const MCInstrDesc &MID = TII->get(NewOpc); in ExtractHoistableLoad()
DTwoAddressInstructionPass.cpp1106 unsigned NewOpc = in TryInstructionTransform() local
1111 if (NewOpc != 0) { in TryInstructionTransform()
1112 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc); in TryInstructionTransform()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp353 unsigned NewOpc = N->getOpcode(); in PromoteIntRes_FP_TO_XINT() local
363 NewOpc = ISD::FP_TO_SINT; in PromoteIntRes_FP_TO_XINT()
365 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); in PromoteIntRes_FP_TO_XINT()