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Searched refs:OpSize (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/Target/X86/
DX86InstrSystem.td64 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize;
78 "in{w}\t{%dx, %ax|AX, DX}", [], IIC_IN_RR>, OpSize;
88 "in{w}\t{$port, %ax|AX, $port}", [], IIC_IN_RI>, OpSize;
98 "out{w}\t{%ax, %dx|DX, AX}", [], IIC_OUT_RR>, OpSize;
108 "out{w}\t{%ax, $port|$port, AX}", [], IIC_OUT_IR>, OpSize;
114 def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>, OpSize;
159 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize;
166 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize;
173 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize;
180 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize;
[all …]
DX86InstrShiftRotate.td25 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize;
42 OpSize;
57 "shl{w}\t$dst", [], IIC_SR>, OpSize;
75 OpSize;
91 OpSize;
110 OpSize;
127 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize;
142 IIC_SR>, OpSize;
157 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize;
174 OpSize;
[all …]
DX86InstrVMX.td20 "invept\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
23 "invept\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
27 "invvpid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
30 "invvpid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
35 "vmclear\t$vmcs", []>, OpSize, TB;
DX86InstrFormats.td97 class OpSize { bit hasOpSizePrefix = 1; }
319 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1]));
329 let Predicates = !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]);
337 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1]));
380 // PDI - SSE2 instructions with TB and OpSize prefixes.
381 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
383 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
403 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
407 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
420 OpSize, Requires<[HasAVX]>;
[all …]
DX86InstrControl.td29 [], IIC_RET>, OpSize;
35 [], IIC_RET_IMM>, OpSize;
39 "{l}ret{w|f}", [], IIC_RET>, OpSize;
45 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize;
124 "ljmp{w}\t{$seg, $off|$off, $seg}", [], IIC_JMP_FAR_PTR>, OpSize;
132 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize;
166 IIC_CALL_FAR_PTR>, OpSize;
173 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize;
181 "callw\t$dst", []>, OpSize;
DX86InstrInfo.td741 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
768 IIC_POP_REG16>, OpSize;
772 IIC_POP_REG>, OpSize;
774 IIC_POP_MEM>, OpSize;
780 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
787 IIC_PUSH_REG>, OpSize;
791 IIC_PUSH_REG>, OpSize;
794 OpSize;
803 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize;
808 OpSize;
[all …]
DX86InstrExtension.td17 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
24 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
45 TB, OpSize;
49 TB, OpSize;
68 TB, OpSize;
72 TB, OpSize;
DX86InstrSSE.td806 TB, OpSize, VEX;
812 TB, OpSize, VEX;
819 TB, OpSize, VEX;
825 TB, OpSize, VEX;
831 TB, OpSize;
837 TB, OpSize;
1151 itin, SSEPackedDouble>, TB, OpSize;
2005 // SSE2 instructions without OpSize prefix
2254 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2261 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
[all …]
DX86InstrArithmetic.td21 "lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize;
61 [], IIC_MUL16_REG>, OpSize; // AX,DX = AX*GR16
87 [], IIC_MUL16_MEM>, OpSize; // AX,DX = AX*[mem16]
104 IIC_IMUL16_RR>, OpSize; // AX,DX = AX*GR16
118 "imul{w}\t$src", [], IIC_IMUL16_MEM>, OpSize;
139 TB, OpSize;
160 TB, OpSize;
187 IIC_IMUL16_RRI>, OpSize;
194 OpSize;
228 OpSize;
[all …]
DX86InstrCMovSetCC.td25 IIC_CMOV16_RR>,TB,OpSize;
46 TB, OpSize;
DX86InstrMMX.td506 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
512 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
515 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
DX86InstrCompiler.td205 [(set GR16:$dst, 0)], IIC_ALU_NONMEM>, OpSize;
245 OpSize;
308 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
320 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
338 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
353 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
648 [], IIC_ALU_NONMEM>, OpSize, LOCK;
727 "inc{w}\t$dst", [], IIC_UNARY_MEM>, OpSize, LOCK;
740 "dec{w}\t$dst", [], IIC_UNARY_MEM>, OpSize, LOCK;
776 [(X86cas addr:$ptr, GR16:$swap, 2)], IIC_CMPX_LOCK>, TB, OpSize, LOCK;
[all …]
DX86CodeEmitter.cpp687 if (TSFlags & X86II::OpSize) in emitOpcodePrefix()
872 if (TSFlags & X86II::OpSize) in emitVEXOpcodePrefix()
DX86ISelLowering.cpp2403 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; in LowerCall() local
2404 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); in LowerCall()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h302 OpSize = 1 << 6, enumerator
DX86MCCodeEmitter.cpp511 if (TSFlags & X86II::OpSize) in EmitVEXOpcodePrefix()
889 if (TSFlags & X86II::OpSize) in EmitOpcodePrefix()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp2527 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; in CalculateTailCallArgDest() local
2528 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); in CalculateTailCallArgDest()
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp9138 int64_t OpSize; in GatherAllAliases() local
9143 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, in GatherAllAliases()
9152 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, in GatherAllAliases()