| /external/llvm/lib/Target/X86/ |
| D | X86InstrCompiler.td | 30 // Random Pseudo Instructions.
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
89 def VAARG_64 : I<0, Pseudo,
106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
116 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
[all …]
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| D | X86InstrFormats.td | 21 def Pseudo : Format<0>; def RawFrm : Format<1>;
151 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
205 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
262 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
265 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
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| /external/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 69 // Pseudo valuetype mapped to the current pointer size to any address space.
73 // Pseudo valuetype to represent "vector of any size"
76 // Pseudo valuetype to represent "float of any format"
79 // Pseudo valuetype to represent "integer of any bit width"
82 // Pseudo valuetype mapped to the current pointer size.
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 368 // Pseudo-instructions:
372 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "",
374 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "",
378 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
383 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "",
391 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
394 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
397 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
400 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
403 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
[all …]
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| D | PPCInstr64Bit.td | 66 def MovePCtoLR8 : Pseudo<(outs), (ins), "", []>,
143 def ATOMIC_LOAD_ADD_I64 : Pseudo<
146 def ATOMIC_LOAD_SUB_I64 : Pseudo<
149 def ATOMIC_LOAD_OR_I64 : Pseudo<
152 def ATOMIC_LOAD_XOR_I64 : Pseudo<
155 def ATOMIC_LOAD_AND_I64 : Pseudo<
158 def ATOMIC_LOAD_NAND_I64 : Pseudo<
162 def ATOMIC_CMP_SWAP_I64 : Pseudo<
167 def ATOMIC_SWAP_I64 : Pseudo<
185 def TCRETURNdi8 :Pseudo< (outs),
[all …]
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 207 // Pseudo instructions.
208 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
213 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
217 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
220 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
242 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
244 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
247 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
258 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
263 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
[all …]
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| D | SparcInstrInfo.h | 30 Pseudo = (1<<0), enumerator
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| /external/chromium/third_party/libjingle/source/ |
| D | CHANGELOG | 45 - Pseudo-TCP support provides TCP-like reliability over a P2PSocket
47 using Pseudo-TCP.
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 100 Pseudo, enumerator
203 return Flags & (1 << MCID::Pseudo); in isPseudo()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 293 // Pseudo-registers representing odd-even pairs of D registers. The even-odd
311 // Pseudo-registers representing 3 consecutive D registers.
322 // Pseudo 256-bit registers to represent pairs of Q registers. These should
327 // Pseudo 256-bit vector register class to model pairs of Q registers
346 // Pseudo 512-bit registers to represent four consecutive Q registers.
350 // Pseudo 512-bit vector register class to model 4 consecutive Q registers
359 // Pseudo-registers representing 2-spaced consecutive D registers.
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| D | ARMInstrFormats.td | 22 def Pseudo : Format<0>;
276 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
317 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
321 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
342 // Pseudo instructions for the code generator.
344 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo,
1410 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain,
1713 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1722 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.td | 444 Operand MemOpnd, bit Pseudo>:
448 let isPseudo = Pseudo;
452 Operand MemOpnd, bit Pseudo>:
456 let isPseudo = Pseudo;
461 bit Pseudo = 0> {
462 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
464 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
473 bit Pseudo = 0> {
474 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
476 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
[all …]
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| D | MipsInstrFormats.td | 31 def Pseudo : Format<0>;
82 // Mips Pseudo Instructions Format
84 MipsInst<outs, ins, asmstr, pattern, IIPseudo, Pseudo> {
89 // Mips32/64 Pseudo Instruction Format
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| D | MipsCodeEmitter.cpp | 383 if ((MI.getDesc().TSFlags & MipsII::FormMask) == MipsII::Pseudo) in emitInstruction()
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 228 Pseudo = 0, enumerator
538 case X86II::Pseudo: in getMemoryOperandNo()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.td | 116 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
119 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
125 def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc),
129 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR16:$src2, i8imm:$cc),
134 def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
137 def Shl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
140 def Sra8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
143 def Sra16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
146 def Srl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
149 def Srl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
[all …]
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| D | MSP430InstrFormats.td | 206 // Pseudo instructions
207 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMBaseInfo.h | 297 Pseudo = 0 << FormShift, enumerator
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsBaseInfo.h | 99 Pseudo = 0, enumerator
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| D | MipsMCCodeEmitter.cpp | 129 if ((TSFlags & MipsII::FormMask) == MipsII::Pseudo) in EncodeInstruction()
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUInstrFormats.td | 288 // Pseudo instructions, like call frames:
291 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
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| /external/llvm/utils/TableGen/ |
| D | PseudoLoweringEmitter.cpp | 58 void evaluateExpansion(Record *Pseudo);
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| D | X86RecognizableInstr.cpp | 53 Pseudo = 0, enumerator
399 if (Form == X86Local::Pseudo || in filter()
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| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 48 def Pseudo : Format<0>; def RawFrm : Format<1>;
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeInstrFormats.td | 82 // Pseudo instruction class
|