| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 93 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
94 ; CHECK: sc $[[R14]], 0($[[R2]])
95 ; CHECK: beq $[[R14]], $zero, $[[BB0]]
124 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
125 ; CHECK: sc $[[R14]], 0($[[R2]])
126 ; CHECK: beq $[[R14]], $zero, $[[BB0]]
156 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
157 ; CHECK: sc $[[R14]], 0($[[R2]])
158 ; CHECK: beq $[[R14]], $zero, $[[BB0]]
185 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R9]]
[all …]
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| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| D | MBlazeBaseInfo.h | 119 case MBlaze::R14 : return 14; in getMBlazeRegisterNumbering()
183 case 14 : return MBlaze::R14; in getMBlazeRegisterFromNumbering()
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUCallingConv.td | 22 R12, R13, R14, R15, R16, R17, R18, R19, R20,
39 R12, R13, R14, R15, R16, R17, R18, R19, R20,
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| D | SPURegisterInfo.cpp | 68 case SPU::R14: return 14; in getRegisterNumbering()
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| D | SPURegisterInfo.td | 38 def R14 : SPUVecReg<14, "$14">, DwarfRegNum<[14]>;
|
| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 93 case X86::EDI: case X86::R14: return 4; in getCompactUnwindRegNum()
117 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: in getSEHRegNum()
346 X86::R12, X86::R13, X86::R14, X86::R15 in getReservedRegs()
640 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegister()
677 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegister()
713 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegister()
765 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegister()
766 return X86::R14; in getX86SubSuperRegister()
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| D | X86CallingConv.td | 244 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
422 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
427 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
|
| D | X86RegisterInfo.td | 138 def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
276 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
308 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
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| /external/kernel-headers/original/asm-x86/ |
| D | ptrace-abi.h | 29 #define R14 8 macro
|
| /external/valgrind/main/VEX/auxprogs/ |
| D | genoffsets.c | 114 GENOFFSET(AMD64,amd64,R14); in foo()
157 GENOFFSET(ARM,arm,R14); in foo()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.h | 171 {PPC::R14, -72}, in getCalleeSavedSpillSlots()
250 {PPC::R14, -140}, in getCalleeSavedSpillSlots()
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| D | PPCCallingConv.td | 129 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
137 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20, VRSAVE,
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| D | PPCRegisterInfo.td | 82 def R14 : GPR<14, "r14">, DwarfRegNum<[-2, 14]>;
116 def X14 : GP8<R14, "r14">, DwarfRegNum<[14, -2]>;
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 19 // i16 are returned in registers R15, R14, R13, R12
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCBaseInfo.h | 45 case R14: case X14: case F14: case V14: case CR3EQ: return 14; in getPPCRegisterNumbering()
|
| /external/valgrind/main/coregrind/m_sigframe/ |
| D | sigframe-arm-linux.c | 152 SC2(lr,R14); in synth_ucontext()
326 REST(lr,R14); in VG_()
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| D | sigframe-amd64-linux.c | 351 SC2(r14,R14); in synth_ucontext()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 78 def R14 : Ri<14, "r14">, DwarfRegNum<[14]>;
110 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>;
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| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 175 ENTRY(R14) \
193 ENTRY(R14) \
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeRegisterInfo.cpp | 77 Reserved.set(MBlaze::R14); in getReservedRegs()
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| D | MBlazeRegisterInfo.td | 56 def R14 : MBlazeGPRReg< 14, "r14">, DwarfRegNum<[14]>;
|
| /external/llvm/test/CodeGen/X86/ |
| D | ghc-cc64.ll | 9 @r2 = external global i64 ; assigned to register: R14
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| D | optimize-max-3.ll | 49 ; CHECK-NEXT: cmpl [[R14:%[a-z0-9]+]], [[BX]]
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 241 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: in getX86RegNum()
314 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: in InitLLVM2SEHRegisterMapping()
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| D | X86BaseInfo.h | 598 case X86::R12: case X86::R13: case X86::R14: case X86::R15: in isX86_64ExtendedReg()
|