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Searched refs:RAX (Results 1 – 25 of 38) sorted by relevance

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/external/llvm/test/CodeGen/X86/
Dabi-isel.ll56 ; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r..]]
57 ; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
85 ; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]]
86 ; DARWIN-64-STATIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
92 ; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]]
93 ; DARWIN-64-DYNAMIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
99 ; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]]
100 ; DARWIN-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
128 ; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
129 ; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]]
[all …]
Dobject-size.ll15 ; X64: movabsq $-1, [[RAX:%r..]]
16 ; X64: cmpq $-1, [[RAX]]
D2009-09-19-earlyclobber.ll4 ; Registers other than RAX, RCX are OK, but they must be different.
D2010-02-12-CoalescerBug-Impdef.ll5 ; After coalescing %RAX with a virtual register, this instruction was rematted:
9 ; This instruction silently defined %RAX, and when rematting removed the
10 ; instruction, the live interval for %RAX was not properly updated. The valno
13 ; The fix is to implicitly define %RAX when coalescing:
15 ; %EAX<def> = MOV32rr %reg1070<kill>, %RAX<imp-def>
Dmisched-new.ll12 ; After coalescing, we have a dead superreg (RAX) definition.
D2010-04-08-CoalescerBug.ll5 ; %RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def>
/external/llvm/lib/Target/X86/
DX86InstrSVM.td35 let Uses = [RAX] in
37 "vmrun\t{%rax|RAX}", []>, TB, Requires<[In64BitMode]>;
43 let Uses = [RAX] in
45 "vmload\t{%rax|RAX}", []>, TB, Requires<[In64BitMode]>;
51 let Uses = [RAX] in
53 "vmsave\t{%rax|RAX}", []>, TB, Requires<[In64BitMode]>;
59 let Uses = [RAX, ECX] in
61 "invlpga\t{%ecx, %rax|RAX, ECX}", []>, TB, Requires<[In64BitMode]>;
DX86InstrArithmetic.td68 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
70 "mul{q}\t$src", // RAX,RDX = RAX*GR64
71 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/],
93 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
95 "mul{q}\t$src", [], IIC_MUL64>; // RAX,RDX = RAX*[mem64]
108 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
110 IIC_IMUL64_RR>; // RAX,RDX = RAX*GR64
123 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
125 "imul{q}\t$src", [], IIC_IMUL64>; // RAX,RDX = RAX*[mem64]
278 // RDX:RAX/r64 = RAX,RDX
[all …]
DX86InstrExtension.td30 let Defs = [RAX], Uses = [EAX] in
32 "{cltq|cdqe}", []>; // RAX = signext(EAX)
34 let Defs = [RAX,RDX], Uses = [RAX] in
36 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
DX86InstrSystem.td16 let Defs = [RAX, RDX] in
20 let Defs = [RAX, RCX, RDX] in
421 let Defs = [RDX, RAX], Uses = [RCX] in
424 let Uses = [RDX, RAX, RCX] in
427 let Uses = [RDX, RAX] in {
444 let Defs = [RAX, RDI], Uses = [RDX, RDI] in
457 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
461 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
DX86RegisterInfo.td121 def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>;
307 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
331 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
333 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
335 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
354 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
358 // to clear upper 32-bits of RAX so is not a NOP.
DX86RegisterInfo.cpp600 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
612 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
649 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
685 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
737 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
738 return X86::RAX; in getX86SubSuperRegister()
DX86MCInstLower.cpp246 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
279 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortMoveForm()
539 OutMI.addOperand(MCOperand::CreateReg(X86::RAX)); in Lower()
DX86CallingConv.td38 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
104 // The X86-Win64 calling convention always returns __m64 values in RAX.
425 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
DX86InstrControl.td242 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
243 let Defs = [RAX, R10, R11, RSP, EFLAGS],
DX86SelectionDAGInfo.cpp106 ValReg = X86::RAX; in EmitTargetCodeForMemset()
DX86FrameLowering.cpp103 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI, in findDeadCallerSavedReg()
168 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX) in emitSPUpdate()
893 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX) in emitPrologue()
1548 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10); in adjustForSegmentedStacks()
/external/llvm/test/MC/Disassembler/X86/
Dintel-syntax.txt30 # CHECK: xchg RAX, R8
42 # CHECK: add RAX, 0
54 # CHECK: adc RAX, 0
66 # CHECK: cmp RAX, 0
78 # CHECK: test RAX, 0
/external/llvm/test/MC/X86/
Dintel-syntax.s19 mov RAX, QWORD PTR [RSP]
25 mov EAX, DWORD PTR [RSP + 4*RAX - 24]
65 mov RAX, QWORD PTR FS:[320]
Dintel-syntax-encoding.s25 mov QWORD PTR [RSP - 16], RAX
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp1199 else if (reg == X86::RAX && (isLods || Name == "lodsq")) in ParseInstruction()
1229 else if (reg == X86::RAX && (isStos || Name == "stosq")) in ParseInstruction()
1322 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1323 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1361 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1362 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1400 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1401 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1437 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1475 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
[all …]
/external/kernel-headers/original/asm-x86/
Dptrace-abi.h39 #define RAX 80 macro
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h161 ENTRY(RAX) \
179 ENTRY(RAX) \
/external/valgrind/main/VEX/auxprogs/
Dgenoffsets.c100 GENOFFSET(AMD64,amd64,RAX); in foo()
/external/valgrind/main/coregrind/m_sigframe/
Dsigframe-amd64-linux.c358 SC2(rax,RAX); in synth_ucontext()

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